;*******************************************************************************
;*           MC9S08GB60 FRAMEWORK INCLUDE FILE FOR ASM8 ASSEMBLER              *
;*******************************************************************************
; FREEWARE, Copyright (c) Tony G. Papadimitriou <tonyp@acm.org>
;*******************************************************************************

                    #Uses     macros.inc
                    #Message  **********************
                    #Message  * Target: MC9S08GB60 *
                    #Message  **********************

                    #HcsOn
                    #NoMMU                        ;MMU not available
#ifdef BOOT
                    #Message  BootROM pre-loaded
  #ifexists tboot.exp
                    #Uses     tboot.exp
  #else
                    #Uses     tboot/tboot.exp
  #endif

#endif

_GB_                def       60
FLL_FACTOR          def       256                 ;dummy to silence generic warning

;*******************************************************************************
;* Author: Tony Papadimitriou - <tonyp@acm.org>
;*         Jim Sibigtroth - Motorola TSPG (Original version)
;*
;* Description: Register and bit name definitions for 9S08GB60
;*
;* Documentation: 9S08GB60 family Data Sheet for register and bit explanations
;* HCS08 Family Reference Manual (HCS08RM1/D) appendix B for explanation of
;* equate files
;*
;* Modified by <tonyp@acm.org> as follows:
;*
;* 1. All bit names for use with BSET/BCLR/BRSET/BRCLR end with a dot (.)
;* 2. All bit names for use as masks end with an underscore (_)
;* 3. ASM8's segments RAM, ROM, XROM, SEG9 (OS8), EEPROM and VECTORS
;*    initialized with appropriate values for immediate use.
;* 4. The assembly-time symbol FLASH_DATA_SIZE optionally defines the protected Flash
;*    as the difference between total flash and FLASH_DATA_SIZE
;*    Based on MC9S08GB60's architecture, FLASH_DATA_SIZE can only take specific
;*    values.  An invalid value will cause an informative assembler error message.
;* 5. ASM8's #MEMORY directive used to define actual Flash space for user code/data
;*
;* Include Files: COMMON.INC
;*
;* Assembler:  ASM8 v9.65+ by Tony G. Papadimitriou <tonyp@acm.org>
;*
;* Revision History: not yet released
;* Rev #     Date      Who     Comments
;* -----  -----------  ------  -------------------------------------------------
;*  1.5    24-Oct-05   T-Pap   Added some aliases
;*  1.4    05-Feb-04   T-Pap   Adapted to ASM8 by <tonyp@acm.org>
;*  1.3    28-Apr-03   J-Sib   SPCO->SPC0, IIAS->IAAS, AN2111 format
;*  1.2    24-Apr-03   J-Sib   correct minor typos in comments
;*  1.1    21-Apr-03   J-Sib   comments and modify for CW 3.0 project
;*  1.0    15-Apr-03   J-Sib   Release version for 9S08GB60
;*******************************************************************************

; **** Memory Map and Interrupt Vectors ****************************************

HighRegs            def       $1800               ; start of high page registers
HighRegs_End        def       $182B               ; end of high page registers

; **** Input/Output (I/O) Ports ************************************************

PTAD                def       $00,1               ; I/O port A data register
PORTA               def       PTAD,1
PTAPE               def       $01,1               ; I/O port A pullup enable controls
PTAPUE              def       PTAPE,1
PTASE               def       $02,1               ; I/O port A slew rate control register
PTADD               def       $03,1               ; I/O port A data direction register
DDRA                def       $03,1               ; I/O port A data direction register
PTBD                def       $04,1               ; I/O port B data register
PORTB               def       PTBD,1
PTBPE               def       $05,1               ; I/O port B pullup enable controls
PTBPUE              def       PTBPE,1
PTBSE               def       $06,1               ; I/O port B slew rate control register
PTBDD               def       $07,1               ; I/O port B data direction register
DDRB                def       $07,1               ; I/O port B data direction register
PTCD                def       $08,1               ; I/O port C data register
PORTC               def       PTCD,1
PTCPE               def       $09,1               ; I/O port C pullup enable controls
PTCPUE              def       PTCPE,1
PTCSE               def       $0A,1               ; I/O port C slew rate control register
PTCDD               def       $0B,1               ; I/O port C data direction register
DDRC                def       $0B,1               ; I/O port C data direction register
PTDD                def       $0C,1               ; I/O port D data register
PORTD               def       PTDD,1
PTDPE               def       $0D,1               ; I/O port D pullup enable controls
PTDPUE              def       PTDPE,1
PTDSE               def       $0E,1               ; I/O port D slew rate control register
PTDDD               def       $0F,1               ; I/O port D data direction register
DDRD                def       $0F,1               ; I/O port D data direction register
PTED                def       $10,1               ; I/O port E data register
PORTE               def       $10,1               ; I/O port E data register
PTEPE               def       $11,1               ; I/O port E pullup enable controls
PTEPUE              def       PTEPE,1
PTESE               def       $12,1               ; I/O port E slew rate control register
PTEDD               def       $13,1               ; I/O port E data direction register
DDRE                def       $13,1               ; I/O port E data direction register
PTFD                def       $40,1               ; I/O port F data register
PORTF               def       $40,1               ; I/O port F data register
PTFPE               def       $41,1               ; I/O port F pullup enable controls
PTFPUE              def       PTFPE,1
PTFSE               def       $42,1               ; I/O port F slew rate control register
PTFDD               def       $43,1               ; I/O port F data direction register
DDRF                def       $43,1               ; I/O port F data direction register
PTGD                def       $44,1               ; I/O port G data register
PORTG               def       $44,1               ; I/O port G data register
PTGPE               def       $45,1               ; I/O port G pullup enable controls
PTGPUE              def       PTGPE,1
PTGSE               def       $46,1               ; I/O port G slew rate control register
PTGDD               def       $47,1               ; I/O port G data direction register
DDRG                def       $47,1               ; I/O port G data direction register

; **** Interrupt Request Module (IRQ) ******************************************

IRQSC               def       $14,1               ; IRQ status and control register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

IRQEDG.             def       5                   ; (bit #5) IRQ pin edge sensitivity
IRQPE.              def       4                   ; (bit #4) IRQ pin enable (PTB5)
IRQF.               def       3                   ; (bit #3) IRQ flag
IRQACK.             def       2                   ; (bit #2) acknowledge IRQ flag
IRQIE.              def       1                   ; (bit #1) IRQ pin interrupt enable
IRQMOD.             def       0                   ; (bit #0) IRQ mode

; bit position masks

IRQEDG_             def       %00100000           ; IRQ pin edge sensitivity
IRQPE_              def       %00010000           ; IRQ pin enable (PTB5)
IRQF_               def       %00001000           ; IRQ flag
IRQACK_             def       %00000100           ; acknowledge IRQ flag
IRQIE_              def       %00000010           ; IRQ pin interrupt enable
IRQMOD_             def       %00000001           ; IRQ mode

; **** Keyboard Interrupt Module (KBI) *****************************************

KBISC               def       $16                 ; KBI status and control register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

KBEDG7.             def       7                   ; rise-hi/fall-low for KBIP7 pin
KBEDG6.             def       6                   ; rise-hi/fall-low for KBIP6 pin
KBEDG5.             def       5                   ; rise-hi/fall-low for KBIP5 pin
KBEDG4.             def       4                   ; rise-hi/fall-low for KBIP4 pin
KBF.                def       3                   ; KBI flag
KBACK.              def       2                   ; acknowledge
KBIE.               def       1                   ; KBI interrupt enable
KBIMOD.             def       0                   ; KBI mode select

; bit position masks

KBEDG7_             def       %10000000           ; rise-hi/fall-low for KBIP7 pin
KBEDG6_             def       %01000000           ; rise-hi/fall-low for KBIP6 pin
KBEDG5_             def       %00100000           ; rise-hi/fall-low for KBIP5 pin
KBEDG4_             def       %00010000           ; rise-hi/fall-low for KBIP4 pin
KBF_                def       %00001000           ; KBI flag
KBACK_              def       %00000100           ; acknowledge
KBIE_               def       %00000010           ; KBI interrupt enable
KBIMOD_             def       %00000001           ; KBI mode select

KBIPE               def       $17                 ; KBI pin enable controls

; **** Serial Communications Interface 1&2 (SCI1 & SCI2) ***********************

SCI1BD              def       $18,2               ; SCI1 baud rate register
SCI1BDH             def       $18,1               ; SCI1 baud rate register (high)
SCI1BDL             def       $19,1               ; SCI1 baud rate register (low byte)
SCI2BD              def       $20,2               ; SCI2 baud rate register
SCI2BDH             def       $20,1               ; SCI2 baud rate register (high)
SCI2BDL             def       $21,1               ; SCI2 baud rate register (low byte)
SCI1C1              def       $1A,1               ; SCI1 control register 1
SCI2C1              def       $22,1               ; SCI2 control register 1

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

LOOPS.              def       7                   ; (bit #7) loopback mode
SCISWAI.            def       6                   ; (bit #6) SCI stop in wait
RSRC.               def       5                   ; (bit #5) receiver source
M.                  def       4                   ; (bit #4) 9/8 bit data
WAKE.               def       3                   ; (bit #3) wake by addr mark/idle
ILT.                def       2                   ; (bit #2) idle line type; stop/start
PE.                 def       1                   ; (bit #1) parity enable
PT.                 def       0                   ; (bit #0) parity type

; bit position masks

LOOPS_              def       %10000000           ; loopback mode select
SCISWAI_            def       %01000000           ; SCI stops in wait mode
RSRC_               def       %00100000           ; receiver source
M_                  def       %00010000           ; 9/8 bit data
WAKE_               def       %00001000           ; wakeup by addr mark/idle
ILT_                def       %00000100           ; idle line type; after stop/start
PE_                 def       %00000010           ; parity enable
PT_                 def       %00000001           ; parity type even/odd

SCI1C2              def       $1B,1               ; SCI1 control register 2
SCI2C2              def       $23,1               ; SCI2 control register 2

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

TIE.                def       7                   ; (bit #7) transmit interrupt enable
TCIE.               def       6                   ; (bit #6) TC interrupt enable
RIE.                def       5                   ; (bit #5) receive interrupt enable
ILIE.               def       4                   ; (bit #4) idle line interrupt enable
TE.                 def       3                   ; (bit #3) transmitter enable
RE.                 def       2                   ; (bit #2) receiver enable
RWU.                def       1                   ; (bit #1) receiver wakeup engage
SBK.                def       0                   ; (bit #0) send break

; bit position masks

TIE_                def       %10000000           ; transmit interrupt (TDRE) enable
TCIE_               def       %01000000           ; transmit complete interrupt enable
RIE_                def       %00100000           ; receive interrupt (RDRF) enable
ILIE_               def       %00010000           ; idle line interrupt (ILIE) enable
TE_                 def       %00001000           ; transmitter enable
RE_                 def       %00000100           ; receiver enable
RWU_                def       %00000010           ; receiver wakeup engage
SBK_                def       %00000001           ; send break characters

SCI1S1              def       $1C,1               ; SCI1 status register 1
SCI2S1              def       $24,1               ; SCI2 status register 1

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

TDRE.               def       7                   ; (bit #7) Tx data register empty
TC.                 def       6                   ; (bit #6) transmit complete
RDRF.               def       5                   ; (bit #5) Rx data register full
IDLE.               def       4                   ; (bit #4) idle line detected
OR.                 def       3                   ; (bit #3) Rx over run
NF.                 def       2                   ; (bit #2) Rx noise flag
FE.                 def       1                   ; (bit #1) Rx framing error
PF.                 def       0                   ; (bit #0) Rx parity failed

; bit position masks

TDRE_               def       %10000000           ; transmit data register empty
TC_                 def       %01000000           ; transmit complete
RDRF_               def       %00100000           ; receive data register full
IDLE_               def       %00010000           ; idle line detected
OR_                 def       %00001000           ; receiver over run
NF_                 def       %00000100           ; receiver noise flag
FE_                 def       %00000010           ; receiver framing error
PF_                 def       %00000001           ; received parity failed

SCI1S2              def       $1D,1               ; SCI1 status register 2
SCI2S2              def       $25,1               ; SCI2 status register 2

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

RAF.                def       0                   ; (bit #0) Rx active flag

; bit position masks

RAF_                def       %00000001           ; receiver active flag

SCI1C3              def       $1E,1               ; SCI1 control register 3
SCI2C3              def       $26,1               ; SCI2 control register 3

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

R8.                 def       7                   ; (bit #7) 9th Rx bit
T8.                 def       6                   ; (bit #6) 9th Tx bit
TXDIR.              def       5                   ; (bit #5) TxD pin direction?
ORIE.               def       3                   ; (bit #3) Rx over run int. enable
NEIE.               def       2                   ; (bit #2) Rx noise flag int. enable
FEIE.               def       1                   ; (bit #1) Rx framing error int. enable
PEIE.               def       0                   ; (bit #0) Rx parity error int. enable

; bit position masks

R8_                 def       %10000000           ; 9th receive data bit
T8_                 def       %01000000           ; 9th transmit data bit
TXDIR_              def       %00100000           ; transmit pin direction?
ORIE_               def       %00001000           ; receiver over run int. enable
NEIE_               def       %00000100           ; receiver noise flag int. enable
FEIE_               def       %00000010           ; receiver framing error int. enable
PEIE_               def       %00000001           ; received parity error int. enable

SCI1D               def       $1F,1               ; SCI1 data register (low byte)
SCI2D               def       $27,1               ; SCI2 data register (low byte)

; **** Serial Peripheral Interface (SPI) ***************************************

SPIC1               def       $28,1               ; SPI control register 1

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

SPIE.               def       7                   ; (bit #7) SPI interrupt enable
SPE.                def       6                   ; (bit #6) SPI enable
SPTIE.              def       5                   ; (bit #5) Tx error interrupt enable
MSTR.               def       4                   ; (bit #4) master/slave
CPOL.               def       3                   ; (bit #3) clock polarity
CPHA.               def       2                   ; (bit #2) clock phase
SSOE.               def       1                   ; (bit #1) SS output enable
LSBFE.              def       0                   ; (bit #0) LSB-first enable

; bit position masks

SPIE_               def       %10000000           ; SPI interrupt enable
SPE_                def       %01000000           ; SPI enable
SPTIE_              def       %00100000           ; SPI Tx error interrupt enable
MSTR_               def       %00010000           ; master/slave
CPOL_               def       %00001000           ; clock polarity
CPHA_               def       %00000100           ; clock phase
SSOE_               def       %00000010           ; slave select output enable
LSBFE_              def       %00000001           ; LSB-first enable

SPIC2               def       $29,1               ; SPI control register 2

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

MODFEN.             def       4                   ; (bit #4) mode fault enable
BIDIROE.            def       3                   ; (bit #3) bi-directional enable
SPISWAI.            def       1                   ; (bit #1) SPI stops in wait
SPC0.               def       0                   ; (bit #0) SPI pin 0 control

; bit position masks

MODFEN_             def       %00010000           ; mode fault enable
BIDIROE_            def       %00001000           ; bi-directional operation enable
SPISWAI_            def       %00000010           ; SPI stops in wait mode
SPC0_               def       %00000001           ; SPI pin 0 control

SPIBR               def       $2A,1               ; SPI baud rate select

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

SPPR2.              def       6                   ; (bit #6) SPI baud rate prescale
SPPR1.              def       5                   ; (bit #5) "
SPPR0.              def       4                   ; (bit #4) "
SPR2.               def       2                   ; (bit #2) SPI rate selact
SPR1.               def       1                   ; (bit #1) "
SPR0.               def       0                   ; (bit #0) "

; bit position masks

SPPR2_              def       %01000000           ; SPI baud rate prescale
SPPR1_              def       %00100000           ; "
SPPR0_              def       %00010000           ; "
SPR2_               def       %00000100           ; SPI rate select
SPR1_               def       %00000010           ; "
SPR0_               def       %00000001           ; "

SPIS                def       $2B,1               ; SPI status register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

SPRF                @pin      SPIS,7              ; (bit #7) SPI Rx full flag
SPTEF               @pin      SPIS,5              ; (bit #5) SPI Transmit Buffer Empty Flag
MODF                @pin      SPIS,4              ; (bit #4) mode fault flag

SPID                def       $2D,1               ; SPI data register

; **** Analog-to-Digital Converter Module (ATD) ********************************

ATDC                def       $50,1               ; atd control tegister

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

ATDPU.              def       7                   ; (bit #7) ATD power up
DJM.                def       6                   ; (bit #6) justification mode; rt/left
RES8.               def       5                   ; (bit #5) ATD resolution select
SGN.                def       4                   ; (bit #4) signed result select
PRS3.               def       3                   ; (bit #3) prescaler rate select (high)
PRS2.               def       2                   ; (bit #2) prescaler rate select
PRS1.               def       1                   ; (bit #1) prescaler rate select
PRS0.               def       0                   ; (bit #0) prescaler rate select (low)

; bit position masks

ATDPU_              def       %10000000           ; ATD power up
DJM_                def       %01000000           ; data justification mode; right/left
RES8_               def       %00100000           ; ATD resolution select
SGN_                def       %00010000           ; signed result select
PRS3_               def       %00001000           ; prescaler rate select (high)
PRS2_               def       %00000100           ; prescaler rate select
PRS1_               def       %00000010           ; prescaler rate select
PRS0_               def       %00000001           ; prescaler rate select (low)

ATDSC               def       $51,1               ; atd ststus and control register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

CCF.                def       7                   ; (bit #7) conversion complete flag
ATDIE.              def       6                   ; (bit #6) ATD interrupt enable
ATDCO.              def       5                   ; (bit #5) ATD continuous conversion
ATDCH4.             def       4                   ; (bit #4) ATD input channel select (high)
ATDCH3.             def       3                   ; (bit #3) ATD input channel select
ATDCH2.             def       2                   ; (bit #2) ATD input channel select
ATDCH1.             def       1                   ; (bit #1) ATD input channel select
ATDCH0.             def       0                   ; (bit #0) ATD input channel select (low)

; bit position masks

CCF_                def       %10000000           ; conversion complete flag
ATDIE_              def       %01000000           ; ATD interrupt enable
ATDCO_              def       %00100000           ; ATD continuous conversion
ATDCH4_             def       %00010000           ; ATD input channel select (high)
ATDCH3_             def       %00001000           ; prescaler rate select
ATDCH2_             def       %00000100           ; prescaler rate select
ATDCH1_             def       %00000010           ; prescaler rate select
ATDCH0_             def       %00000001           ; prescaler rate select (low)

ATDPE               def       $54,1               ; ATD pin enable register
ATDR                def       $52,2               ; ATD result register
ATDRH               def       $52,1               ; ATD result register (high)
ATDRL               def       $53,1               ; ATD result register (low)

; **** Inter-Integrated Circuit Module (IIC) ***********************************

IICA                def       $58,1               ; IIC address register

IICF                def       $59,1               ; IIC frequency divider register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

MULT1.              def       7                   ; (bit #7) IIC multiply factor (high)
MULT0.              def       6                   ; (bit #6) IIC multiply factor (low)
ICR5.               def       5                   ; (bit #5) IIC Divider and Hold bit-5
ICR4.               def       4                   ; (bit #4) IIC Divider and Hold bit-4
ICR3.               def       3                   ; (bit #3) IIC Divider and Hold bit-3
ICR2.               def       2                   ; (bit #2) IIC Divider and Hold bit-2
ICR1.               def       1                   ; (bit #1) IIC Divider and Hold bit-1
ICR0.               def       0                   ; (bit #0) IIC Divider and Hold bit-0

; bit position masks

MULT1_              def       %10000000           ; IIC multiply factor (high)
MULT0_              def       %01000000           ; IIC multiply factor (low)
ICR5_               def       %00100000           ; IIC Divider and Hold bit-5
ICR4_               def       %00010000           ; IIC Divider and Hold bit-4
ICR3_               def       %00001000           ; IIC Divider and Hold bit-3
ICR2_               def       %00000100           ; IIC Divider and Hold bit-2
ICR1_               def       %00000010           ; IIC Divider and Hold bit-1
ICR0_               def       %00000001           ; IIC Divider and Hold bit-0

IICC                def       $5A,1               ; IIC control register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

IICEN.              def       7                   ; (bit #7) IIC enable bit
IICIE.              def       6                   ; (bit #6) IIC interrupt enable bit
MST.                def       5                   ; (bit #5) IIC master mode select bit
TX.                 def       4                   ; (bit #4) IIC transmit mode select bit
TXAK.               def       3                   ; (bit #3) IIC transmit acknowledge bit
RSTA.               def       2                   ; (bit #2) IIC repeat start bit

; bit position masks

IICEN_              def       %10000000           ; IIC enable
IICIE_              def       %01000000           ; IIC interrupt enable bit
MST_                def       %00100000           ; IIC master mode select bit
TX_                 def       %00010000           ; IIC transmit mode select bit
TXAK_               def       %00001000           ; IIC transmit acknowledge bit
RSTA_               def       %00000100           ; IIC repeat start bit

IICS                def       $5B,1               ; IIC status register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

TCF.                def       7                   ; (bit #7) IIC transfer complete flag bit
IAAS.               def       6                   ; (bit #6) IIC addressed as slave bit
BUSY.               def       5                   ; (bit #5) IIC bus busy bit
ARBL.               def       4                   ; (bit #4) IIC arbitration lost bit
SRW.                def       2                   ; (bit #2) IIC slave read/write bit
IICIF.              def       1                   ; (bit #1) IIC interrupt flag bit
RXAK.               def       0                   ; (bit #0) IIC receive acknowledge bit

; bit position masks

TCF_                def       %10000000           ; IIC transfer complete flag bit
IAAS_               def       %01000000           ; IIC addressed as slave bit
BUSY_               def       %00100000           ; IIC bus busy bit
ARBL_               def       %00010000           ; IIC arbitration lost bit
SRW_                def       %00000100           ; IIC slave read/write bit
IICIF_              def       %00000010           ; IIC interrupt flag bit
RXAK_               def       %00000001           ; IIC receive acknowledge bit

IICD                def       $5C,1               ; IIC data I/O register bits 7:0

; **** Timer/PWM Module 1 (TPM1) ***** TPM1 has 3 channels *********************
; **** Timer/PWM Module 2 (TPM2) ***** TPM2 has 5 channels *********************

TPM1SC              def       $30,1               ; TPM1 status and control register
TPMSC               def       TPM1SC,1
TPM2SC              def       $60,1               ; TPM2 status and control register

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

TOF.                def       7                   ; (bit #7) tomer overflow flag
TOIE.               def       6                   ; (bit #6) TOF interrupt enable
CPWMS.              def       5                   ; (bit #5) centered PWM select
CLKSB.              def       4                   ; (bit #4) clock select bits
CLKSA.              def       3                   ; (bit #3) "
PS2.                def       2                   ; (bit #2) prescaler bits
PS1.                def       1                   ; (bit #1) "
PS0.                def       0                   ; (bit #0) "

; bit position masks

TOF_                def       %10000000           ; timer overflow flag
TOIE_               def       %01000000           ; timer overflow interrupt enable
CPWMS_              def       %00100000           ; center-aligned PWM select
CLKSB_              def       %00010000           ; clock source select bits
CLKSA_              def       %00001000           ; "
PS2_                def       %00000100           ; prescaler bits
PS1_                def       %00000010           ; "
PS0_                def       %00000001           ; "

TPM1CNT             def       $31,2               ; TPM1 counter
TPM1CNTH            def       $31,1               ; TPM1 counter (high half)
TPM1CNTL            def       $32,1               ; TPM1 counter (low half)
TPM1MOD             def       $33,2               ; TPM1 modulo register
TPM1MODH            def       $33,1               ; TPM1 modulo register (high half)
TPM1MODL            def       $34,1               ; TPM1 modulo register(low half)

TPMCNT              def       TPM1CNTH,2
TPMCNTH             def       TPM1CNTH,1
TPMCNTL             def       TPM1CNTL,1
TPMMOD              def       TPM1MODH,2
TPMMODH             def       TPM1MODH,1
TPMMODL             def       TPM1MODL,1

TPM2CNT             def       $61,2               ; TPM2 counter
TPM2CNTH            def       $61,1               ; TPM2 counter (high half)
TPM2CNTL            def       $62,1               ; TPM2 counter (low half)
TPM2MOD             def       $63,2               ; TPM2 modulo register
TPM2MODH            def       $63,1               ; TPM2 modulo register (high half)
TPM2MODL            def       $64,1               ; TPM2 modulo register(low half)

TPM1C0SC            def       $35,1               ; TPM1 channel 0 status and control
TPMC0SC             def       TPM1C0SC,1
TPM2C0SC            def       $65,1               ; TPM2 channel 0 status and control

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

CHnF.               equ       7                   ; Channel n Flag
CHnIE.              equ       6                   ; Channel n Interrupt Enable
MSnB.               equ       5                   ; Mode Select B for TPM Channel n
MSnA.               equ       4                   ; Mode Select A for TPM Channel n
ELSnB.              equ       3                   ; Edge/Level Select Bits
ELSnA.              equ       2

CHnF_               equ       1<CHnF.
CHnIE_              equ       1<CHnIE.
MSnB_               equ       1<MSnB.
MSnA_               equ       1<MSnA.
ELSnB_              equ       1<ELSnB.
ELSnA_              equ       1<ELSnA.

CH0F.               def       7                   ; (bit #7) channel 0 flag
CH0IE.              def       6                   ; (bit #6) ch 0 interrupt enable
MS0B.               def       5                   ; (bit #5) mode select B
MS0A.               def       4                   ; (bit #4) mode select A
ELS0B.              def       3                   ; (bit #3) edge/level select B
ELS0A.              def       2                   ; (bit #2) edge/level select A

; bit position masks

CH0F_               def       %10000000           ; channel 0 flag
CH0IE_              def       %01000000           ; ch 0 interrupt enable
MS0B_               def       %00100000           ; mode select B
MS0A_               def       %00010000           ; mode select A
ELS0B_              def       %00001000           ; edge/level select B
ELS0A_              def       %00000100           ; edge/level select A

TPM1C0VH            def       $36,2               ; TPM1 channel 0 value register
TPM1C0VH            def       $36,1               ; TPM1 channel 0 value register (high)
TPM1C0VL            def       $37,1               ; TPM1 channel 0 value register (low)
TPMC0V              def       TPM1C0VH,2
TPMC0VH             def       TPM1C0VH,1
TPMC0VL             def       TPM1C0VL,1

TPM2C0V             def       $66,2               ; TPM2 channel 0 value register
TPM2C0VH            def       $66,1               ; TPM2 channel 0 value register (high)
TPM2C0VL            def       $67,1               ; TPM2 channel 0 value register (low)

TPM1C1SC            def       $38,1               ; TPM1 channel 1 status and control
TPMC1SC             def       TPM1C1SC,1
TPM2C1SC            def       $68,1               ; TPM2 channel 1 status and control

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

CH1F.               def       7                   ; (bit #7) channel 1 flag
CH1IE.              def       6                   ; (bit #6) ch 1 interrupt enable
MS1B.               def       5                   ; (bit #5) mode select B
MS1A.               def       4                   ; (bit #4) mode select A
ELS1B.              def       3                   ; (bit #3) edge/level select B
ELS1A.              def       2                   ; (bit #2) edge/level select A

; bit position masks

CH1F_               def       %10000000           ; channel 1 flag
CH1IE_              def       %01000000           ; ch 1 interrupt enable
MS1B_               def       %00100000           ; mode select B
MS1A_               def       %00010000           ; mode select A
ELS1B_              def       %00001000           ; edge/level select B
ELS1A_              def       %00000100           ; edge/level select A

TPM1C1V             def       $39,2               ; TPM1 channel 1 value register
TPM1C1VH            def       $39,1               ; TPM1 channel 1 value register (high)
TPM1C1VL            def       $3A,1               ; TPM1 channel 1 value register (low)
TPMC1V              def       TPM1C1VH,2
TPMC1VH             def       TPM1C1VH,1
TPMC1VL             def       TPM1C1VL,1

TPM2C1V             def       $69,2               ; TPM2 channel 1 value register
TPM2C1VH            def       $69,1               ; TPM2 channel 1 value register (high)
TPM2C1VL            def       $6A,1               ; TPM2 channel 1 value register (low)

TPM1C2SC            def       $3B,1               ; TPM1 channel 2 status and control
TPMC2SC             def       TPM1C2SC,1
TPM2C2SC            def       $6B,1               ; TPM2 channel 2 status and control

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

CH2F.               def       7                   ; (bit #7) channel 2 flag
CH2IE.              def       6                   ; (bit #6) ch 2 interrupt enable
MS2B.               def       5                   ; (bit #5) mode select B
MS2A.               def       4                   ; (bit #4) mode select A
ELS2B.              def       3                   ; (bit #3) edge/level select B
ELS2A.              def       2                   ; (bit #2) edge/level select A

; bit position masks

CH2F_               def       %10000000           ; channel 2 flag
CH2IE_              def       %01000000           ; ch 2 interrupt enable
MS2B_               def       %00100000           ; mode select B
MS2A_               def       %00010000           ; mode select A
ELS2B_              def       %00001000           ; edge/level select B
ELS2A_              def       %00000100           ; edge/level select A

TPM1C2V             def       $3C,2               ; TPM1 channel 2 value register
TPM1C2VH            def       $3C,1               ; TPM1 channel 2 value register (high)
TPM1C2VL            def       $3D,1               ; TPM1 channel 2 value register (low)
TPMC2V              def       TPM1C2VH,2
TPMC2VH             def       TPM1C2VH,1
TPMC2VL             def       TPM1C2VL,1

TPM2C2V             def       $6C,2               ; TPM2 channel 1 value register
TPM2C2VH            def       $6C,1               ; TPM2 channel 1 value register (high)
TPM2C2VL            def       $6D,1               ; TPM2 channel 1 value register (low)

TPM2C3SC            def       $6E,1               ; TPM2 channel 3 status and control

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

CH3F.               def       7                   ; (bit #7) channel 3 flag
CH3IE.              def       6                   ; (bit #6) ch 3 interrupt enable
MS3B.               def       5                   ; (bit #5) mode select B
MS3A.               def       4                   ; (bit #4) mode select A
ELS3B.              def       3                   ; (bit #3) edge/level select B
ELS3A.              def       2                   ; (bit #2) edge/level select A

; bit position masks

CH3F_               def       %10000000           ; channel 3 flag
CH3IE_              def       %01000000           ; ch 3 interrupt enable
MS3B_               def       %00100000           ; mode select B
MS3A_               def       %00010000           ; mode select A
ELS3B_              def       %00001000           ; edge/level select B
ELS3A_              def       %00000100           ; edge/level select A

TPM2C3V             def       $6F,2               ; TPM2 channel 1 value register
TPM2C3VH            def       $6F,1               ; TPM2 channel 1 value register (high)
TPM2C3VL            def       $70,1               ; TPM2 channel 1 value register (low)

TPM2C4SC            def       $71,1               ; TPM2 channel 4 status and control

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

CH4F.               def       7                   ; (bit #7) channel 4 flag
CH4IE.              def       6                   ; (bit #6) ch 4 interrupt enable
MS4B.               def       5                   ; (bit #5) mode select B
MS4A.               def       4                   ; (bit #4) mode select A
ELS4B.              def       3                   ; (bit #3) edge/level select B
ELS4A.              def       2                   ; (bit #2) edge/level select A

; bit position masks

CH4F_               def       %10000000           ; channel 4 flag
CH4IE_              def       %01000000           ; ch 4 interrupt enable
MS4B_               def       %00100000           ; mode select B
MS4A_               def       %00010000           ; mode select A
ELS4B_              def       %00001000           ; edge/level select B
ELS4A_              def       %00000100           ; edge/level select A

TPM2C4VH            def       $72,1               ; TPM2 channel 1 value register (high)
TPM2C4VL            def       $73,1               ; TPM2 channel 1 value register (low)

; **** Internal Clock Generator Module (ICG) ***********************************

ICGC1               def       $48,1               ; ICG control register 1

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

RANGE_SEL.          def       6                   ; (bit #6) frequency range select
REFS.               def       5                   ; (bit #5) reference select
CLKS1.              def       4                   ; (bit #4) clock select bit 1
CLKS0.              def       3                   ; (bit #3) clock select bit 0
OSCSTEN.            def       2                   ; (bit #2) oscillator runs in stop

; bit position masks

RANGE_SEL_          def       %01000000           ; frequency range select
REFS_               def       %00100000           ; reference select
CLKS1_              def       %00010000           ; clock mode select (bit-1)
CLKS0_              def       %00001000           ; clock mode select (bit 0)
OSCSTEN_            def       %00000100           ; enable oscillator in stop mode

ICGC2               def       $49,1               ; ICG control register 2

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

LOLRE.              def       7                   ; (bit #7) loss of lock reset enable
MFD2.               def       6                   ; (bit #6) multiplication factor div
MFD1.               def       5                   ; (bit #5) "
MFD0.               def       4                   ; (bit #4) "
LOCRE.              def       3                   ; (bit #3) loss of clock reset enable
RFD2.               def       2                   ; (bit #2) reference divider
RFD1.               def       1                   ; (bit #1) "
RFD0.               def       0                   ; (bit #0) "

; bit position masks

LOLRE_              def       %10000000           ; loss of lock reset enable
MFD2_               def       %01000000           ; multiplication factor divider
MFD1_               def       %00100000           ; "
MFD0_               def       %00010000           ; "
LOCRE_              def       %00001000           ; loss of clock reset enable
RFD2_               def       %00000100           ; reference divider bits
RFD1_               def       %00000010           ; "
RFD0_               def       %00000001           ; "

ICGS1:              def       $4A,1               ; ICG status register 1

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

CLKST1.             def       7                   ; (bit #7) clock mode status 1
CLKST0.             def       6                   ; (bit #6) clock mode status 0
REFST.              def       5                   ; (bit #5) reference clock status
LOLS.               def       4                   ; (bit #4) loss of lock status
LOCK.               def       3                   ; (bit #3) FLL lock status
LOCS.               def       2                   ; (bit #2) loss of clock status
ERCS.               def       1                   ; (bit #1) ext ref clk status
ICGIF.              def       0                   ; (bit #0) ICG interrupt flag

; bit position masks

CLKST1_             def       %10000000           ; clock mode status 1
CLKST0_             def       %01000000           ; clock mode status 0
REFST_              def       %00100000           ; reference clock status
LOLS_               def       %00010000           ; loss of lock status
LOCK_               def       %00001000           ; FLL lock status
LOCS_               def       %00000100           ; loss of clock status
ERCS_               def       %00000010           ; ext ref clk status
ICGIF_              def       %00000001           ; ICG interrupt flag

ICGS2               def       $4B,1               ; ICG status register 2

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET

DCOS                def       0                   ; (bit #0) DCO Clock Stable

; bit position masks

mDCOS               def       %00000001           ; DCO Clock Stable

ICGFLT              def       $4C,2               ; ICG filter register (upper 4 bits in bits 3:0)
ICGFLTU             def       $4C,1               ; ICG filter register (upper 4 bits in bits 3:0)
ICGFLTL             def       $4D,1               ; ICG filter register (lower 8 bits)

ICGTRM              def       $4E,1               ; ICG trim register

; **** System Integration Module (SIM) *****************************************

SRS                 def       $1800,1             ; SIM reset status register
COP                 def       SRS,1               ; for "STA COP"

; bit position masks

POR_                def       %10000000           ; power-on reset
PIN_                def       %01000000           ; external reset pin
COP_                def       %00100000           ; COP watchdog timed out
ILOP_               def       %00010000           ; illegal opcode
ICG_                def       %00000100           ; illegal address access
LVD_                def       %00000010           ; low-voltage detect

SBDFR               def       $1801,1             ; system BDM reset register

; bit position masks

BDFR_               def       %00000001           ; BDM force reset

SOPT                def       $1802,1             ; SIM options register (write once)

; bit position masks

COPE_               def       %10000000           ; COP watchdog enable
COPT_               def       %01000000           ; COP time-out select
STOPE_              def       %00100000           ; stop enable
BKGDPE_             def       %00000010           ; BDM pin enable

SDID                def       $1806,2             ; system device identification 1 register (read-only)
SDIDH               def       $1806,1             ; system device identification 1 register (read-only)
SDIDL               def       $1807,1             ; rev3,2,1,0 + 12-bit ID. GB60 ID = $002

; bit position masks within SDIDH

REV3_               def       %10000000           ; device revision identification (high)
REV2_               def       %01000000           ; device revision identification
REV1_               def       %00100000           ; device revision identification
REV0_               def       %00010000           ; device revision identification (low)

; **** Power Management and Control Module (PMC) *******************************

SRTISC              def       $1808,1             ; System RTI ststus and control register

; bit position masks

RTIF_               def       %10000000           ; real-time interrupt flag
RTIACK_             def       %01000000           ; real-time interrupt acknowledge
RTICLKS_            def       %00100000           ; real-time interrupt clock select
RTIE_               def       %00010000           ; real-time interrupt enable
RTIS2_              def       %00000100           ; real-time interrupt delay select (high)
RTIS1_              def       %00000010           ; real-time interrupt delay select
RTIS0_              def       %00000001           ; real-time interrupt delay select (low)

SPMSC1              def       $1809,1             ; System power management status and control 1 register

; bit position masks

LVDF_               def       %10000000           ; low voltage detect flag
LVDACK_             def       %01000000           ; LVD interrupt acknowledge
LVDIE_              def       %00100000           ; LVD interrupt enable
LVDRE_              def       %00010000           ; LVD reset enable (write once bit)
LVDSE_              def       %00001000           ; LDV stop enable (write once bit)
LVDE_               def       %00000100           ; LVD enable (write once bit)

SPMSC2              def       $180A,1             ; System power management status and control 2 register

; bit position masks

LVWF_               def       %10000000           ; low voltage warning flag
LVWACK_             def       %01000000           ; low voltage warning acknowledge
LVDV_               def       %00100000           ; low voltage detect voltage select
LVWV_               def       %00010000           ; low voltage warning voltage select
PPDF_               def       %00001000           ; partial power down flag
PPDACK_             def       %00000100           ; partial power down acknowledge
PDC_                def       %00000010           ; power down control
PPDC_               def       %00000001           ; partial power down control

; **** Debug Module (DBG) ******************************************************

DBGCA               def       $1810,2             ; DBG comparator register A
DBGCAH              def       $1810,1             ; DBG comparator register A (high)
DBGCAL              def       $1811,1             ; DBG comparator register A (low)
DBGCB               def       $1812,2             ; DBG comparator register B
DBGCBH              def       $1812,1             ; DBG comparator register B (high)
DBGCBL              def       $1813,1             ; DBG comparator register B (low)
DBGF                def       $1814,2             ; DBG FIFO register
DBGFH               def       $1814,1             ; DBG FIFO register (high)
DBGFL               def       $1815,1             ; DBG FIFO register (low)

DBGC                def       $1816,1             ; DBG control register

; bit position masks

DBGEN_              def       %10000000           ; debug module enable
ARM_                def       %01000000           ; arm control
TAG_                def       %00100000           ; tag/force select
BRKEN_              def       %00010000           ; break enable
RWA_                def       %00001000           ; R/W compare A value
RWAEN_              def       %00000100           ; R/W compare A enable
RWB_                def       %00000010           ; R/W compare B value
RWBEN_              def       %00000001           ; R/W compare B enable

DBGT                def       $1817,1             ; DBG trigger register

; bit position masks

TRGSEL_             def       %10000000           ; trigger on opcode/access
BEGIN_              def       %01000000           ; begin/end trigger
TRG3_               def       %00001000           ; trigger mode bits
TRG2_               def       %00000100           ; "
TRG1_               def       %00000010           ; "
TRG0_               def       %00000001           ; "

DBGS                def       $1818,1             ; DBG status register

; bit position masks

AF_                 def       %10000000           ; trigger A match flag
BF_                 def       %01000000           ; trigger B match flag
ARMF_               def       %00100000           ; arm flag
CNT3_               def       %00001000           ; count of items in FIFO (high)
CNT2_               def       %00000100           ; "
CNT1_               def       %00000010           ; "
CNT0_               def       %00000001           ; count of items in FIFO (low)

; **** Flash Module (FLASH) ****************************************************

FCDIV               def       $1820,1             ; Flash clock divider register

; bit position masks

DIVLD_              def       %10000000           ; clock divider loaded
PRDIV8_             def       %01000000           ; enable prescale by 8

FOPT                def       $1821,1             ; Flash options register

; bit position masks

KEYEN_              def       %10000000           ; enable backdoor key to security
FNORED_             def       %01000000           ; Vector redirection enable
SEC01_              def       %00000010           ; security state code (high)
SEC00_              def       %00000001           ; security state code (low)

FCNFG               def       $1823,1             ; Flash configuration register

; bit position masks

KEYACC_             def       %00100000           ; enable security key writing

FPROT               def       $1824,1             ; Flash protection register

; bit position masks

FPOPEN_             def       %10000000           ; open unprotected flash for program/erase
FPDIS_              def       %01000000           ; flash protection disable
FPS2_               def       %00100000           ; flash protect size select (high)
FPS1_               def       %00010000           ; flash protect size select
FPS0_               def       %00001000           ; flash protect size select (low)

FSTAT               def       $1825,1             ; Flash status register

; bit position masks

FCBEF_              def       %10000000           ; flash command buffer empty flag
FCCF_               def       %01000000           ; flash command complete flag
FPVIOL_             def       %00100000           ; flash protection violation
FACCERR_            def       %00010000           ; flash access error
FBLANK_             def       %00000100           ; flash verified as all blank (erased =$ff) flag

FCMD                def       $1826,1             ; Flash command register

; command codes for flash programming/erasure to be used with FCMD register

Blank_              def       $05                 ; Blank Check command
ByteProg_           def       $20                 ; Byte Program command
BurstProg_          def       $25                 ; Burst Program command
PageErase_          def       $40                 ; Page Erase command
MassErase_          def       $41                 ; Mass Erase command

; **** Flash non-volatile register images **************************************

NVBACKKEY           def       $FFB0,1             ; 8-byte backdoor comparison key
                                                  ; comparison key in $FFB0 through $FFB7

; following 2 registers transfered from flash to working regs at reset

NVPROT              def       $FFBD,1             ; NV flash protection byte

; NVPROT transfers to FPROT on reset

NVICGTRIM           def       $FFBE,1             ; NV ICG Trim Setting

; ICG trim value measured during factory test. User software optionally
; copies to ICGTRM during initialization.

NVOPT               def       $FFBF,1             ; NV flash options byte

; NVFEOPT transfers to FOPT on reset

; **** END OF ORIGINAL DEFINITIONS *********************************************

_9S08GB60_          def       *                   ;Tells us this INCLUDE has been used

FLASH_PAGE_SIZE     def       512                 ; minimum that must be erased at once

          #if FLASH_PAGE_SIZE <> 512
                    #Error    FLASH_PAGE_SIZE should be fixed at 512
          #endif

FLASH_DATA_SIZE     def       0                   ; default: no runtime flash storage

VECTORS             def       $FFCC               ; start of fixed vectors
          #ifdef RVECTORS
VECTORS             set       RVECTORS
          #endif

;--- Vectors
                    #temp     VECTORS
Vrti                next      :temp,2             ; RTI (periodic interrupt) vector
Viic                next      :temp,2             ; IIC vector
Vadc                next      :temp,2             ; analog to digital conversion vector
Vkeyboard           next      :temp,2             ; keyboard vector
Vsci2tx             next      :temp,2             ; SCI2 transmit vector
Vsci2rx             next      :temp,2             ; SCI2 receive vector
Vsci2err            next      :temp,2             ; SCI2 error vector
Vsci1tx             next      :temp,2             ; SCI1 transmit vector
Vsci1rx             next      :temp,2             ; SCI1 receive vector
Vsci1err            next      :temp,2             ; SCI1 error vector
Vspi                next      :temp,2             ; SPI vector
Vtpm2ovf            next      :temp,2             ; TPM2 overflow vector
Vtpm2ch4            next      :temp,2             ; TPM2 channel 4 vector
Vtpm2ch3            next      :temp,2             ; TPM2 channel 3 vector
Vtpm2ch2            next      :temp,2             ; TPM2 channel 2 vector
Vtpm2ch1            next      :temp,2             ; TPM2 channel 1 vector
Vtpm2ch0            next      :temp,2             ; TPM2 channel 0 vector
Vtpm1ovf            next      :temp,2             ; TPM1 overflow vector
Vtpm1ch2            next      :temp,2             ; TPM1 channel 2 vector
Vtpm1ch1            next      :temp,2             ; TPM1 channel 1 vector
Vtpm1ch0            next      :temp,2             ; TPM1 channel 0 vector
Vicg                next      :temp,2             ; ICG vector
Vlvd                next      :temp,2             ; low voltage detect vector
Virq                next      :temp,2             ; IRQ pin vector
Vswi                next      :temp,2             ; SWI vector
Vreset              next      :temp,2             ; reset vector

; Aliases for certain vectors

Vtpmovf             def       Vtpm1ovf,2
Vtpmch2             def       Vtpm1ch2,2
Vtpmch1             def       Vtpm1ch1,2
Vtpmch0             def       Vtpm1ch0,2

TRUE_ROM            def       $1080               ; start of 60K flash (extra ROM)

;-------------------------------------------------------------------------------
?                   macro     Size,NVPROT_Mask
#if FLASH_DATA_SIZE = ~1~
?NVPROT_MASK        def       %~2~
#endif
                    endm

                    @?            0,10111000
                    @?         1920,10111000
                    @?        28544,10110000
                    @?        44928,10101000
                    @?        53120,10100000
                    @?        57216,10011000
                    @?        59264,10010000
                    @?        60288,10001000
                    @?        60800,10000000
                    @?        61312,11000000
;-------------------------------------------------------------------------------

          #ifdef BOOTROM
?NVPROT_MASK        set       %11000000
          #endif

          #ifndef ?NVPROT_MASK
                    #Error    FLASH_DATA_SIZE ({FLASH_DATA_SIZE}) not 0,1920,28544,44928,53120,57216,59264,60288,60800,61312
          #endif

EEPROM              def       TRUE_ROM
EEPROM_END          def       EEPROM+FLASH_DATA_SIZE-1

          #if EEPROM_END <= HighRegs_End
ROM                 def       HighRegs_End+1
          #endif
ROM                 def       EEPROM_END+1

ROM_END             def       $FFAF               ; end of all flash (before NV register and fixed vectors)

#ifdef BOOT&BOOTROM
ROM_END             set       BOOTROM-1
#endif

RAM                 def       $0080               ; start of 4096 byte RAM
RAM_END             def       $00FF               ; last zero-page RAM location

XRAM                equ       $0100               ; WAS: $0101 before v8.55
XRAM_END            def       $107F               ; last true RAM location

#ifdef BOOTRAM_END
RAM                 set       BOOTRAM_END         ; start of 4096 byte RAM
#endif

FLASH_START         def       EEPROM_END+1
FLASH_END           def       ROM_END

          #ifdef BOOT&BOOTROM
FLASH_END           set       BOOTROM-1
          #endif

SERIAL_NUMBER       def       $FFA0               ; start of optional S/N (FFA0-FFAD)

#ifndef MHZ
  #ifndef KHZ
HZ                  def       8000000             ;8MHz PEMicro Simulator
HZ                  def       15552000            ;243KHz (IRG) *64
  #endif
#endif
;-------------------------------------------------------------------------------
                    #Uses     common.inc
;-------------------------------------------------------------------------------

;                   @pin      SPI_SS,PORTE,2      ; SPI /SS pin

                    #EEPROM
                    org       EEPROM

                    #DATA


          #ifndef BOOT
                    org       NVPROT              ; NV flash protection byte
                    fcb       ?NVPROT_MASK        ; NVPROT transfers to FPROT on reset

          #ifndef NVOPT_VALUE
                    #Message  Using default NVOPT_VALUE (no vector redirection)
          #endif
NVOPT_VALUE         def       %11000010           ; NVFEOPT transfers to FOPT on reset
                             ; |||||||+---------- SEC00 \ 00:secure  10:unsecure
                             ; ||||||+----------- SEC01 / 01:secure  11:secure
                             ; ||++++------------ Not Used (Always 0)
                             ; |+---------------- FNORED - Vector Redirection Disable (No Redirection)
                             ; +----------------- KEYEN - Backdoor key mechanism enable

                    org       NVOPT               ; NV flash options byte
                    fcb       NVOPT_VALUE         ; NVFEOPT transfers to FOPT on reset
          #endif
;                   org       NVICGTRIM           ; NV ICG Trim Setting
;                   fcb       ??                  ; ICG trim value measured during factory test. User software optionally
;                                                 ; copies to ICGTRM during initialization.
                    #VECTORS
                    org       VECTORS

                    #RAM
                    org       RAM

                    #XRAM
                    org       XRAM

                    #ROM
                    org       ROM

                    #MEMORY   ROM       ROM_END
                    #MEMORY   NVBACKKEY NVBACKKEY+7
                    #MEMORY   NVPROT
                    #MEMORY   NVOPT
                    #MEMORY   VECTORS   VECTORS|$00FF

          #if EEPROM < HighRegs
                    #MEMORY   EEPROM    HighRegs-1
          #endif

          #if EEPROM_END > HighRegs_End
                    #MEMORY   HighRegs_End+1 EEPROM_END
          #endif

          #ifdef RVECTORS
                    #MEMORY   RVECTORS  RVECTORS|$00FF
          #endif

          #ifdef CRC_LOCATION
                    #MEMORY   CRC_LOCATION CRC_LOCATION+1
          #endif