;*******************************************************************************
;*           MC9S08QE128 FRAMEWORK INCLUDE FILE FOR ASM8 ASSEMBLER             *
;*******************************************************************************
; FREEWARE, Copyright (c) Tony G. Papadimitriou <tonyp@acm.org>
;*******************************************************************************

                    #Uses     macros.inc
                    #Message  ***********************
                    #Message  * Target: MC9S08QE128 *
                    #Message  ***********************

                    #HcsOn
#ifdef BOOT
                    #Message  TBoot pre-loaded
          #ifexists tboot.exp
                    #Uses     tboot.exp
          #else
                    #Uses     tboot/tboot128.exp
          #endif


          #ifdef OS8PRELOADED
                    #Undef    OS8PRELOADED
          #endif
#endif

#ifdef OS8PRELOADED
                    #Message  BootROM with OS8 pre-loaded

          #ifndef BOOTROM
  #ifexists bootrom.exp
                    #Uses     bootrom.exp
  #else
                    #Uses     bootrom/bootrom.exp
  #endif
          #endif

#endif

_QE_                def       128
_QE128_             def       *

;*******************************************************************************
;* Author: Tony Papadimitriou - <tonyp@acm.org>
;*         Jim Sibigtroth - Motorola TSPG (Original version)
;*
;* Description: Register and bit name definitions for 9S08QE128
;*
;* Documentation: 9S08QE128 family Data Sheet for register and bit explanations
;* HCS08 Family Reference Manual (HCS08RM1/D) appendix B for explanation of
;* equate files
;*
;* Modified by <tonyp@acm.org> as follows:
;*
;* 1. All bit names for use with BSET/BCLR/BRSET/BRCLR end with a dot (.)
;* 2. All bit names for use as masks end with an underscore (_)
;* 3. ASM8's segments RAM, ROM, XROM, SEG9 (OS8), EEPROM and VECTORS
;*    initialized with appropriate values for immediate use.
;* 4. The assembly-time symbol FLASH_DATA_SIZE optionally defines the protected Flash
;*    as the difference between total flash and FLASH_DATA_SIZE
;*    Based on MC9S08QE128's architecture, FLASH_DATA_SIZE can only take specific
;*    values.  An invalid value will cause an informative assembler error message.
;* 5. ASM8's #MEMORY directive used to define actual Flash space for user code/data
;*
;* Include Files: COMMON.INC
;*
;* Assembler:  ASM8 v9.70+ by Tony G. Papadimitriou <tonyp@acm.org>
;*
;* Revision History: not yet released
;* Rev #     Date      Who     Comments
;* -----  -----------  ------  -------------------------------------------------
;*  1.5    24-Oct-05   T-Pap   Added some aliases
;*  1.4    05-Feb-04   T-Pap   Adapted to ASM8 by <tonyp@acm.org>
;*  1.3    28-Apr-03   J-Sib   SPCO->SPC0, IIAS->IAAS, AN2111 format
;*  1.2    24-Apr-03   J-Sib   correct minor typos in comments
;*  1.1    21-Apr-03   J-Sib   comments and modify for CW 3.0 project
;*  1.0    15-Apr-03   J-Sib   Release version for 9S08QE128
;*******************************************************************************

; **** Memory Map and Interrupt Vectors ****************************************

HighRegs            equ       $1800               ; start of high page registers
HighRegs_End        equ       $187F               ; end of high page registers

; **** Input/Output (I/O) Ports ************************************************

PORTA               equ       $00,1               ; I/O port A data register
DDRA                equ       $01,1               ; I/O port A data direction register
PORTB               equ       $02,1               ; I/O port B data register
DDRB                equ       $03,1               ; I/O port B data direction register
PORTC               equ       $04,1               ; I/O port C data register
DDRC                equ       $05,1               ; I/O port C data direction register
PORTD               equ       $06,1               ; I/O port D data register
DDRD                equ       $07,1               ; I/O port D data direction register
PORTE               equ       $08,1               ; I/O port E data register
DDRE                equ       $09,1               ; I/O port E data direction register
PORTF               equ       $0A,1               ; I/O port F data register
DDRF                equ       $0B,1               ; I/O port F data direction register

KBI1SC              equ       $0C,1               ; KBI status and control register
KBI1PE              equ       $0D,1               ; KBI pin enable controls
KBI1ES              equ       $0E,1               ; KBI edge select

IRQSC               equ       $0F,1               ; IRQ status and control register

ADCSC1              equ       $10,1               ; A/D status & control register 1
ADCSC2              equ       $11,1               ; A/D status & control register 2
ADCR                equ       $12,2               ; A/D data result register
ADCRH               equ       $12,1               ; A/D data result register (high)
ADCRL               equ       $13,1               ; A/D data result register (low)
ADCCV               equ       $14,2               ; A/D compare value register
ADCCVH              equ       $14,1               ; A/D compare value register (high)
ADCCVL              equ       $15,1               ; A/D compare value register (low)
ADCCFG              equ       $16,1               ; A/D configuration register

APCTL1              equ       $17,1
APCTL2              equ       $18,1
APCTL3              equ       $19,1

ACMP1SC             equ       $1A,1
ACMP2SC             equ       $1B,1

PORTG               equ       $1C,1
DDRG                equ       $1D,1
PORTH               equ       $1E,1
DDRH                equ       $1F,1

SCI1BD              equ       $20,2               ; SCI1 baud rate register
SCI1BDH             equ       $20,1               ; SCI1 baud rate register (high)
SCI1BDL             equ       $21,1               ; SCI1 baud rate register (low)
SCI1C1              equ       $22,1               ; SCI1 control register 1
SCI1C2              equ       $23,1               ; SCI1 control register 2
SCI1S1              equ       $24,1               ; SCI1 status register 1
SCI1S2              equ       $25,1               ; SCI1 status register 2
SCI1C3              equ       $26,1               ; SCI1 control register 3
SCI1D               equ       $27,1               ; SCI1 data register

SPI1C1              equ       $28,1               ; SPI1 control register 1
SPI1C2              equ       $29,1               ; SPI1 control register 2
SPI1BR              equ       $2A,1               ; SPI1 baud rate select
SPI1S               equ       $2B,1               ; SPI1 status register
SPI1D               equ       $2D,1               ; SPI1 data register

SPIC1               equ       SPI1C1,1
SPIC2               equ       SPI1C2,1
SPIBR               equ       SPI1BR,1
SPIS                equ       SPI1S,1
SPID                equ       SPI1D,1

PORTJ               equ       $2E,1
DDRJ                equ       $2F,1

IIC1A               equ       $30,1               ; IIC1 address register
IIC1F               equ       $31,1               ; IIC1 frequency divider register
IIC1C1              equ       $32,1               ; IIC1 control register 1
IIC1S               equ       $33,1               ; IIC1 status register
IIC1D               equ       $34,1               ; IIC1 data register
IIC1C2              equ       $35,1               ; IIC1 control register 2

ICSC1               equ       $38,1
ICSC2               equ       $39,1
ICSTRM              equ       $3A,1
ICSSC               equ       $3B,1

KBI2SC              equ       $3C,1               ; KBI status and control register
KBI2PE              equ       $3D,1               ; KBI pin enable controls
KBI2ES              equ       $3E,1               ; KBI edge select

TPM1SC              equ       $40,1               ; TPM1 status and control register
TPM1CNT             equ       $41,2               ; TPM1 counter
TPM1CNTH            equ       $41,1               ; TPM1 counter (high half)
TPM1CNTL            equ       $42,1               ; TPM1 counter (low half)
TPM1MOD             equ       $43,2               ; TPM1 modulo register
TPM1MODH            equ       $43,1               ; TPM1 modulo register (high half)
TPM1MODL            equ       $44,1               ; TPM1 modulo register(low half)
TPM1C0SC            equ       $45,1               ; TPM1 channel 0 status and control
TPM1C0V             equ       $46,2               ; TPM1 channel 0 value register
TPM1C0VH            equ       $46,1               ; TPM1 channel 0 value register (high)
TPM1C0VL            equ       $47,1               ; TPM1 channel 0 value register (low)
TPM1C1SC            equ       $48,1               ; TPM1 channel 1 status and control
TPM1C1V             equ       $49,2               ; TPM1 channel 1 value register
TPM1C1VH            equ       $49,1               ; TPM1 channel 1 value register (high)
TPM1C1VL            equ       $4A,1               ; TPM1 channel 1 value register (low)
TPM1C2SC            equ       $4B,1               ; TPM1 channel 2 status and control
TPM1C2V             equ       $4C,2               ; TPM1 channel 2 value register
TPM1C2VH            equ       $4C,1               ; TPM1 channel 2 value register (high)
TPM1C2VL            equ       $4D,1               ; TPM1 channel 2 value register (low)

TPMSC               equ       TPM1SC,1            ; TPM1 status and control register
TPMCNT              equ       TPM1CNTH,2          ; TPM1 counter
TPMCNTH             equ       TPM1CNTH,1          ; TPM1 counter (high half)
TPMCNTL             equ       TPM1CNTL,1          ; TPM1 counter (low half)
TPMMOD              equ       TPM1MODH,2          ; TPM1 modulo register
TPMMODH             equ       TPM1MODH,1          ; TPM1 modulo register (high half)
TPMMODL             equ       TPM1MODL,1          ; TPM1 modulo register(low half)
TPMC0SC             equ       TPM1C0SC,1          ; TPM1 channel 0 status and control
TPMC0V              equ       TPM1C0VH,2          ; TPM1 channel 0 value register
TPMC0VH             equ       TPM1C0VH,1          ; TPM1 channel 0 value register (high)
TPMC0VL             equ       TPM1C0VL,1          ; TPM1 channel 0 value register (low)
TPMC1SC             equ       TPM1C1SC,1          ; TPM1 channel 1 status and control
TPMC1V              equ       TPM1C1VH,2          ; TPM1 channel 1 value register
TPMC1VH             equ       TPM1C1VH,1          ; TPM1 channel 1 value register (high)
TPMC1VL             equ       TPM1C1VL,1          ; TPM1 channel 1 value register (low)
TPMC2SC             equ       TPM1C2SC,1          ; TPM1 channel 2 status and control
TPMC2V              equ       TPM1C2VH,2          ; TPM1 channel 2 value register
TPMC2VH             equ       TPM1C2VH,1          ; TPM1 channel 2 value register (high)
TPMC2VL             equ       TPM1C2VL,1          ; TPM1 channel 2 value register (low)

TPM2SC              equ       $50,1               ; TPM2 status and control register
TPM2CNT             equ       $51,2               ; TPM2 counter
TPM2CNTH            equ       $51,1               ; TPM2 counter (high half)
TPM2CNTL            equ       $52,1               ; TPM2 counter (low half)
TPM2MOD             equ       $53,2               ; TPM2 modulo register
TPM2MODH            equ       $53,1               ; TPM2 modulo register (high half)
TPM2MODL            equ       $54,1               ; TPM2 modulo register(low half)
TPM2C0SC            equ       $55,1               ; TPM2 channel 0 status and control
TPM2C0V             equ       $56,2               ; TPM2 channel 0 value register
TPM2C0VH            equ       $56,1               ; TPM2 channel 0 value register (high)
TPM2C0VL            equ       $57,1               ; TPM2 channel 0 value register (low)
TPM2C1SC            equ       $58,1               ; TPM2 channel 1 status and control
TPM2C1V             equ       $59,2               ; TPM2 channel 1 value register
TPM2C1VH            equ       $59,1               ; TPM2 channel 1 value register (high)
TPM2C1VL            equ       $5A,1               ; TPM2 channel 1 value register (low)
TPM2C2SC            equ       $5B,1               ; TPM2 channel 2 status and control
TPM2C2V             equ       $5C,2               ; TPM2 channel 2 value register
TPM2C2VH            equ       $5C,1               ; TPM2 channel 2 value register (high)
TPM2C2VL            equ       $5D,1               ; TPM2 channel 2 value register (low)

TPM3SC              equ       $60,1               ; TPM3 status and control register
TPM3CNT             equ       $61,2               ; TPM3 counter
TPM3CNTH            equ       $61,1               ; TPM3 counter (high half)
TPM3CNTL            equ       $62,1               ; TPM3 counter (low half)
TPM3MOD             equ       $63,2               ; TPM3 modulo register
TPM3MODH            equ       $63,1               ; TPM3 modulo register (high half)
TPM3MODL            equ       $64,1               ; TPM3 modulo register(low half)
TPM3C0SC            equ       $65,1               ; TPM3 channel 0 status and control
TPM3C0V             equ       $66,2               ; TPM3 channel 0 value register
TPM3C0VH            equ       $66,1               ; TPM3 channel 0 value register (high)
TPM3C0VL            equ       $67,1               ; TPM3 channel 0 value register (low)
TPM3C1SC            equ       $68,1               ; TPM3 channel 1 status and control
TPM3C1V             equ       $69,2               ; TPM3 channel 1 value register
TPM3C1VH            equ       $69,1               ; TPM3 channel 1 value register (high)
TPM3C1VL            equ       $6A,1               ; TPM3 channel 1 value register (low)
TPM3C2SC            equ       $6B,1               ; TPM3 channel 2 status and control
TPM3C2V             equ       $6C,2               ; TPM3 channel 2 value register
TPM3C2VH            equ       $6C,1               ; TPM3 channel 2 value register (high)
TPM3C2VL            equ       $6D,1               ; TPM3 channel 2 value register (low)
TPM3C3SC            equ       $6E,1               ; TPM3 channel 3 status and control
TPM3C3V             equ       $6F,2               ; TPM3 channel 3 value register
TPM3C3VH            equ       $6F,1               ; TPM3 channel 3 value register (high)
TPM3C3VL            equ       $70,1               ; TPM3 channel 3 value register (low)
TPM3C4SC            equ       $71,1               ; TPM3 channel 4 status and control
TPM3C4V             equ       $72,2               ; TPM3 channel 4 value register
TPM3C4VH            equ       $72,1               ; TPM3 channel 4 value register (high)
TPM3C4VL            equ       $73,1               ; TPM3 channel 4 value register (low)
TPM3C5SC            equ       $74,1               ; TPM3 channel 5 status and control
TPM3C5V             equ       $75,2               ; TPM3 channel 5 value register
TPM3C5VH            equ       $75,1               ; TPM3 channel 5 value register (high)
TPM3C5VL            equ       $76,1               ; TPM3 channel 5 value register (low)

;--- MMU related ---

PPAGE               equ       $78,1
LAP2                equ       $79,1
LAP1                equ       $7A,1
LAP0                equ       $7B,1
LWP                 equ       $7C,2
LBP                 equ       $7D,1
LB                  equ       $7E,1
LAPAB               equ       $7F,1
LAP210              equ       LAP2,3              ; alias for LAP2 .. LAP0

;---

SRS                 equ       $1800,1             ; SIM reset status register
COP                 equ       SRS,1               ; for "STA COP"

SBDFR               equ       $1801,1             ; system BDM reset register
SOPT1               equ       $1802,1             ; SIM options register 1
SOPT                equ       SOPT1,1
SOPT2               equ       $1803,1             ; SIM options register 2
SDID                equ       $1806,2             ; system device identification 1 register (read-only)
SDIDH               equ       $1806,1             ; system device identification 1 register (read-only)
SDIDL               equ       $1807,1             ; rev3,2,1,0 + 12-bit ID. QE128 ID = $002

SPMSC1              equ       $1808,1             ; System power management status and control 1 register
SPMSC2              equ       $1809,1             ; System power management status and control 2 register
SPMSC3              equ       $180B,1             ; System power management status and control 3 register

SCGC1               equ       $180E,1
SCGC2               equ       $180F,1

DBGCA               equ       $1810,2             ; DBG comparator register A
DBGCAH              equ       $1810,1             ; DBG comparator register A (high)
DBGCAL              equ       $1811,1             ; DBG comparator register A (low)
DBGCB               equ       $1812,2             ; DBG comparator register B
DBGCBH              equ       $1812,1             ; DBG comparator register B (high)
DBGCBL              equ       $1813,1             ; DBG comparator register B (low)
DBGCC               equ       $1814,2             ; DBG comparator register C
DBGCCH              equ       $1814,1             ; DBG comparator register C (high)
DBGCCL              equ       $1815,1             ; DBG comparator register C (low)
DBGF                equ       $1816,2             ; DBG FIFO register
DBGFH               equ       $1816,1             ; DBG FIFO register (high)
DBGFL               equ       $1817,1             ; DBG FIFO register (low)
DBGCAX              equ       $1818,1
DBGCBX              equ       $1819,1
DBGCCX              equ       $181A,1
DBGFX               equ       $181B,1
DBGC                equ       $181C,1
DBGT                equ       $181D,1             ; DBG trigger register
DBGS                equ       $181E,1             ; DBG status register
DBGCNT              equ       $181F,1

FCDIV               equ       $1820,1             ; Flash clock divider register
FOPT                equ       $1821,1             ; Flash options register
FCNFG               equ       $1823,1             ; Flash configuration register
FPROT               equ       $1824,1             ; Flash protection register
FSTAT               equ       $1825,1             ; Flash status register
FCMD                equ       $1826,1             ; Flash command register

RTCSC               equ       $1830,1
RTCCNT              equ       $1831,1
RTCMOD              equ       $1832,1

SPI2C1              equ       $1838,1             ; SPI2 control register 1
SPI2C2              equ       $1839,1             ; SPI2 control register 2
SPI2BR              equ       $183A,1             ; SPI2 baud rate select
SPI2S               equ       $183B,1             ; SPI2 status register
SPI2D               equ       $183D,1             ; SPI2 data register

PTAPUE              equ       $1840,1             ; I/O port A pullup enable controls
PTAPE               equ       PTAPUE,1            ; -//- (alias)
PTASE               equ       $1841,1             ; I/O port A slew rate control register
PTADS               equ       $1842,1             ; I/O port A drive strength

PTBPUE              equ       $1844,1             ; I/O port B pullup enable controls
PTBPE               equ       PTBPUE,1            ; -//- (alias)
PTBSE               equ       $1845,1             ; I/O port B slew rate control register
PTBDS               equ       $1846,1             ; I/O port B drive strength

PTCPUE              equ       $1848,1             ; I/O port C pullup enable controls
PTCSE               equ       $1849,1             ; I/O port C slew rate control register
PTCDS               equ       $184A,1             ; I/O port C drive strength

PTDPUE              equ       $184C,1             ; I/O port D pullup enable controls
PTDSE               equ       $184D,1             ; I/O port D slew rate control register
PTDDS               equ       $184E,1             ; I/O port D drive strength

PTEPUE              equ       $1850,1             ; I/O port E pullup enable controls
PTESE               equ       $1851,1             ; I/O port E slew rate control register
PTEDS               equ       $1852,1             ; I/O port E drive strength

PTFPUE              equ       $1854,1             ; I/O port F pullup enable controls
PTFSE               equ       $1855,1             ; I/O port F slew rate control register
PTFDS               equ       $1856,1             ; I/O port F drive strength

PTGPUE              equ       $1858,1             ; I/O port G pullup enable controls
PTGSE               equ       $1859,1             ; I/O port G slew rate control register
PTGDS               equ       $185A,1             ; I/O port G drive strength

PTHPUE              equ       $185C,1             ; I/O port H pullup enable controls
PTHSE               equ       $185D,1             ; I/O port H slew rate control register
PTHDS               equ       $185E,1             ; I/O port H drive strength

PTJPUE              equ       $1860,1             ; I/O port J pullup enable controls
PTJSE               equ       $1861,1             ; I/O port J slew rate control register
PTJDS               equ       $1862,1             ; I/O port J drive strength

IIC2A               equ       $1868,1             ; IIC2 address register
IIC2F               equ       $1869,1             ; IIC2 frequency divider register
IIC2C1              equ       $186A,1             ; IIC2 control register 1
IIC2S               equ       $186B,1             ; IIC2 status register
IIC2D               equ       $186C,1             ; IIC2 data register
IIC2C2              equ       $186D,1             ; IIC2 control register 2

SCI2BD              equ       $1870,2             ; SCI2 baud rate register
SCI2BDH             equ       $1870,1             ; SCI2 baud rate register (high)
SCI2BDL             equ       $1871,1             ; SCI2 baud rate register (low)
SCI2C1              equ       $1872,1             ; SCI2 control register 1
SCI2C2              equ       $1873,1             ; SCI2 control register 2
SCI2S1              equ       $1874,1             ; SCI2 status register 1
SCI2S2              equ       $1875,1             ; SCI2 status register 2
SCI2C3              equ       $1876,1             ; SCI2 control register 3
SCI2D               equ       $1877,1             ; SCI2 data register

PTCSET              equ       $1878,1             ; PORTC Set mask
PTESET              equ       $1879,1             ; PORTE Set mask
PTCCLR              equ       $187A,1             ; PORTC Clear mask
PTECLR              equ       $187B,1             ; PORTE Clear mask
PTCTOG              equ       $187C,1             ; PORTC Toggle mask
PTETOG              equ       $187D,1             ; PORTE Toggle mask

;*******************************************************************************
; Bit numbers for use in BCLR, BSET, BRCLR, and BRSET
;*******************************************************************************

;-------------------------------------------------------------------------------
; Flash
;-------------------------------------------------------------------------------

; Flash Clock Divider Register (FCDIV)

FDIVLD.             equ       7                   ; Clock Divider Load Control
PRDIV8.             equ       6                   ; Enable Prescaler by 8

FDIVLD_             equ       1<FDIVLD.
PRDIV8_             equ       1<PRDIV8.

; Flash Options Register (FOPT and NVOPT)

KEYEN1.             equ       7                   ; Backdoor Key Security Enable
KEYEN0.             equ       6
SEC1.               equ       1                   ; Flash Security Bits
SEC0.               equ       0

KEYEN1_             equ       1<KEYEN1.
KEYEN0_             equ       1<KEYEN0.
SEC1_               equ       1<SEC1.
SEC0_               equ       1<SEC0.

; Flash Configuration Register (FCNFG)

KEYACC.             equ       5                   ; Enable Security Key Writing

KEYACC_             equ       1<KEYACC.

; Flash Protection Register (FPROT and NVPROT)

FPOPEN.             equ       0                   ; Flash Protection Open

FPOPEN_             equ       1<FPOPEN.

; Flash Status Register (FSTAT)

FCBEF.              equ       7                   ; Flash Command Buffer Empty Flag
FCCF.               equ       6                   ; Flash Command Complete Interrupt Flag
FPVIOL.             equ       5                   ; Flash Protection Violation Flag
FACCERR.            equ       4                   ; Flash Access Error Flag
FBLANK.             equ       2                   ; Flash Flag Indicating the Erase Verify Operation Status

FCBEF_              equ       1<FCBEF.
FCCF_               equ       1<FCCF.
FPVIOL_             equ       1<FPVIOL.
FACCERR_            equ       1<FACCERR.
FBLANK_             equ       1<FBLANK.

;-------------------------------------------------------------------------------
; IRQ Status and Control (IRQSC)
;-------------------------------------------------------------------------------

IRQPDD.             equ       6                   ; IRQ Pulldown Disable
IRQEDG.             equ       5                   ; IRQ Edge Select
IRQPE.              equ       4                   ; IRQ Pin Enable
IRQF.               equ       3                   ; IRQ Flag
IRQACK.             equ       2                   ; IRQ Acknowledge
IRQIE.              equ       1                   ; IRQ Interrupt Enable
IRQMOD.             equ       0                   ; IRQ Detection Mode

IRQPDD_             equ       1<IRQPDD.
IRQEDG_             equ       1<IRQEDG.
IRQPE_              equ       1<IRQPE.
IRQF_               equ       1<IRQF.
IRQACK_             equ       1<IRQACK.
IRQIE_              equ       1<IRQIE.
IRQMOD_             equ       1<IRQMOD.

;-------------------------------------------------------------------------------
; System Reset Status Register (SRS)
;-------------------------------------------------------------------------------

POR.                equ       7                   ; Power-On Reset
PIN.                equ       6                   ; External Reset Pin
COP.                equ       5                   ; COP Watchdog
ILOP.               equ       4                   ; Illegal Opcode
LVD.                equ       1                   ; Low Voltage Detect

POR_                equ       1<POR.
PIN_                equ       1<PIN.
COP_                equ       1<COP.
ILOP_               equ       1<ILOP.
LVD_                equ       1<LVD.

;-------------------------------------------------------------------------------
; System Options Register 1 (SOPT1)
;-------------------------------------------------------------------------------

COPE.               equ       7                   ; COP Watchdog Enable
COPT.               equ       6                   ; COP Watchdog Timeout
STOPE.              equ       5                   ; Stop Mode Enable
RSTOPE.             equ       2                   ; /RSTO Pin Enable
BKGDPE.             equ       1                   ; Background Debug Mode Pin Enable
RSTPE.              equ       0                   ; /RESET Pin Enable

COPE_               equ       1<COPE.
COPT_               equ       1<COPT.
STOPE_              equ       1<STOPE.
RSTOPE_             equ       1<RSTOPE.
BKGDPE_             equ       1<BKGDPE.
RSTPE_              equ       1<RSTPE.

;-------------------------------------------------------------------------------
; System Options Register 2 (SOPT2)
;-------------------------------------------------------------------------------

COPCLKS.            equ       7                   ; COP Watchdog Clock Select
SPI1PS.             equ       3                   ; SPI1 Pin Select
ACIC2.              equ       2                   ; Analog Comparator 2 to Input Capture Enable
IIC1PS.             equ       1                   ; IIC1 Pin Select
ACIC1.              equ       0                   ; Analog Comparator 1 to Input Capture Enable

COPCLKS_            equ       1<COPCLKS.
SPI1PS_             equ       1<SPI1PS.
ACIC2_              equ       1<ACIC2.
IIC1PS_             equ       1<IIC1PS.
ACIC1_              equ       1<ACIC1.

;-------------------------------------------------------------------------------
; System Power Management Status and Control 1 Register (SPMSC1)
;-------------------------------------------------------------------------------

LVDF.               equ       7                   ; Low-Voltage Detect Flag
LVDACK.             equ       6                   ; Low-Voltage Detect Ackowledge
LVDIE.              equ       5                   ; Low-Voltage Detect Interrupt Enable
LVDRE.              equ       4                   ; Low-Voltage Detect Reset Enable
LVDSE.              equ       3                   ; Low-Voltage Detect Stop Enable
LVDE.               equ       2                   ; Low-Voltage Detect Enable
BGBE.               equ       0                   ; Bandgap Buffer Enable

LVDF_               equ       1<LVDF.
LVDACK_             equ       1<LVDACK.
LVDIE_              equ       1<LVDIE.
LVDRE_              equ       1<LVDRE.
LVDSE_              equ       1<LVDSE.
LVDE_               equ       1<LVDE.
BGBE_               equ       1<BGBE.

;-------------------------------------------------------------------------------
; System Power Management Status and Control 2 Register (SPMSC2)
;-------------------------------------------------------------------------------

LPR.                equ       7                   ; Low Power Regulator Control
LPRS.               equ       6                   ; Low Power Regulator Status
LPWUI.              equ       5                   ; Low Power Wake Up on Interrupt
PPDF.               equ       3                   ; Partial Power Down Flag
PPDACK.             equ       2                   ; Partial Power Down Acknowledge
PPDE.               equ       1                   ; Partial Power Down Enable
PPDC.               equ       0                   ; Partial Power Down Control

LPR_                equ       1<LPR.
LPRS_               equ       1<LPRS.
LPWUI_              equ       1<LPWUI.
PPDF_               equ       1<PPDF.
PPDACK_             equ       1<PPDACK.
PPDE_               equ       1<PPDE.
PPDC_               equ       1<PPDC.

;-------------------------------------------------------------------------------
; System Power Management Status and Control 3 Register (SPMSC3)
;-------------------------------------------------------------------------------

LVWF.               equ       7                   ; Low-Voltage Warning Flag
LVWACK.             equ       6                   ; Low-Voltage Warning Acknowledge
LVDV.               equ       5                   ; Low-Voltage Detect Voltage Select
LVWV.               equ       4                   ; Low-Voltage Warning Voltage Select
LVWIE.              equ       3                   ; Low-Voltage Warning Interrupt Enable

LVWF_               equ       1<LVWF.
LVWACK_             equ       1<LVWACK.
LVDV_               equ       1<LVDV.
LVWV_               equ       1<LVWV.
LVWIE_              equ       1<LVWIE.

;-------------------------------------------------------------------------------
; System Clock Gating Control 1 Register (SCGC1)
;-------------------------------------------------------------------------------

TPM3.               equ       7                   ; TPM3 Clock Gate Control
TPM2.               equ       6                   ; TPM2 Clock Gate Control
TPM1.               equ       5                   ; TPM1 Clock Gate Control
ADC.                equ       4                   ; ADC Clock Gate Control
IIC2.               equ       3                   ; IIC2 Clock Gate Control
IIC1.               equ       2                   ; IIC1 Clock Gate Control
SCI2.               equ       1                   ; SCI2 Clock Gate Control
SCI1.               equ       0                   ; SCI1 Clock Gate Control

TPM3_               equ       1<TPM3.
TPM2_               equ       1<TPM2.
TPM1_               equ       1<TPM1.
ADC_                equ       1<ADC.
IIC2_               equ       1<IIC2.
IIC1_               equ       1<IIC1.
SCI2_               equ       1<SCI2.
SCI1_               equ       1<SCI1.

;-------------------------------------------------------------------------------
; System Clock Gating Control 2 Register (SCGC2)
;-------------------------------------------------------------------------------

DBG.                equ       7                   ; DBG Clock Gate Control
FLS.                equ       6                   ; Flash Register Clock Gate Control
IRQ.                equ       5                   ; IRQ Clock Gate Control
KBI.                equ       4                   ; KBI Clock Gate Control
ACMP.               equ       3                   ; ACMP Clock Gate Control
RTC.                equ       2                   ; RTC Clock Gate Control
SPI2.               equ       1                   ; SPI2 Clock Gate Control
SPI1.               equ       0                   ; SPI1 Clock Gate Control

DBG_                equ       1<DBG.
FLS_                equ       1<FLS.
IRQ_                equ       1<IRQ.
KBI_                equ       1<KBI.
ACMP_               equ       1<ACMP.
RTC_                equ       1<RTC.
SPI2_               equ       1<SPI2.
SPI1_               equ       1<SPI1.

;-------------------------------------------------------------------------------
; KBI Interrupt Status and Control Register (KBIxSC)
;-------------------------------------------------------------------------------

KBF.                equ       3                   ; KBI Interrupt Flag
KBACK.              equ       2                   ; KBI Interrupt Acknowledge
KBIE.               equ       1                   ; KBI Interrupt Enable
KBIMOD.             equ       0                   ; KBI Detection Mode

KBF_                equ       1<KBF.
KBACK_              equ       1<KBACK.
KBIE_               equ       1<KBIE.
KBIMOD_             equ       1<KBIMOD.

;-------------------------------------------------------------------------------
; ACMPx Status and Control Register (ACMPxSC)
;-------------------------------------------------------------------------------

ACME.               equ       7                   ; Analog Comparator Module Enable
ACBGS.              equ       6                   ; Analog Comparator Bandgap Select
ACF.                equ       5                   ; Analog Comparator Flag
ACIE.               equ       4                   ; Analog Comparator Interrupt Enable
ACO.                equ       3                   ; Analog Comparator Output
ACOPE.              equ       2                   ; Analog Comparator Output Pin Enable
ACMOD1.             equ       1                   ; Analog Comparator Mode
ACMOD0.             equ       0

ACME_               equ       1<ACME.
ACBGS_              equ       1<ACBGS.
ACF_                equ       1<ACF.
ACIE_               equ       1<ACIE.
ACO_                equ       1<ACO.
ACOPE_              equ       1<ACOPE.
ACMOD1_             equ       1<ACMOD1.
ACMOD0_             equ       1<ACMOD0.

;-------------------------------------------------------------------------------
; Status and Control Register 1 (ADCSC1)
;-------------------------------------------------------------------------------

COCO.               equ       7                   ; Conversion Complete Flag
AIEN.               equ       6                   ; Interrupt Enable
ADCO.               equ       5                   ; Continuous Conversion Enable

COCO_               equ       1<COCO.
AIEN_               equ       1<AIEN.
ADCO_               equ       1<ADCO.

;-------------------------------------------------------------------------------
; Status and Control Register 2 (ADCSC2)
;-------------------------------------------------------------------------------

ADACT.              equ       7                   ; Conversion Active
ADTRG.              equ       6                   ; Conversion Trigger Select
ACFE.               equ       5                   ; Compare Function Enable
ACFGT.              equ       4                   ; Compare Function Greater Than Enable

ADACT_              equ       1<ADACT.
ADTRG_              equ       1<ADTRG.
ACFE_               equ       1<ACFE.
ACFGT_              equ       1<ACFGT.

;-------------------------------------------------------------------------------
; Configuration Register (ADCCFG)
;-------------------------------------------------------------------------------

ADLPC.              equ       7                   ; Low Power Configuration
ADIV1.              equ       6                   ; Clock Divide Select
ADIV0.              equ       5
ADLSMP.             equ       4                   ; Long Sample Time Configuration
MODE1.              equ       3                   ; Conversion Mode Select
MODE0.              equ       2
ADICLK1.            equ       1                   ; Input Clock Select
ADICLK0.            equ       0

ADLPC_              equ       1<ADLPC.
ADIV1_              equ       1<ADIV1.
ADIV0_              equ       1<ADIV0.
ADLSMP_             equ       1<ADLSMP.
MODE1_              equ       1<MODE1.
MODE0_              equ       1<MODE0.
ADICLK1_            equ       1<ADICLK1.
ADICLK0_            equ       1<ADICLK0.

;-------------------------------------------------------------------------------
; Internal Clock Source (ICS)
;-------------------------------------------------------------------------------

; ICSC1

CLKS1.              equ       7                   ; Clock Source Select
CLKS0.              equ       6
RDIV2.              equ       5                   ; Reference Divider
RDIV1.              equ       4
RDIV0.              equ       3
IREFS.              equ       2                   ; Internal Reference Select
IRCLKEN.            equ       1                   ; Internal Reference Clock Enable
IREFSTEN.           equ       0                   ; Internal Reference Stop Enable

CLKS1_              equ       1<CLKS1.
CLKS0_              equ       1<CLKS0.
RDIV2_              equ       1<RDIV2.
RDIV1_              equ       1<RDIV1.
RDIV0_              equ       1<RDIV0.
IREFS_              equ       1<IREFS.
IRCLKEN_            equ       1<IRCLKEN.
IREFSTEN_           equ       1<IREFSTEN.

; ICSC2

BDIV1.              equ       7                   ; Bus Frequency Divider
BDIV0.              equ       6
RANGE_SEL.          equ       5                   ; Frequency Range Select
HGO.                equ       4                   ; High Gain Oscillator Select
LP.                 equ       3                   ; Low Power Select
EREFS.              equ       2                   ; External Reference Select
ERCLKEN.            equ       1                   ; External Reference Enable
EREFSTEN.           equ       0                   ; External Reference Stop Enable

BDIV1_              equ       1<BDIV1.
BDIV0_              equ       1<BDIV0.
RANGE_SEL_          equ       1<RANGE_SEL.
HGO_                equ       1<HGO.
LP_                 equ       1<LP.
EREFS_              equ       1<EREFS.
ERCLKEN_            equ       1<ERCLKEN.
EREFSTEN_           equ       1<EREFSTEN.

; ICSSC

DRST1.              equ       7                   ; DCO Range Status
DRST0.              equ       6
DRS1.               equ       7                   ; DCO Range Select
DRS0.               equ       6
DMX32.              equ       5                   ; DCO Maximum frequency with 32.768KHz reference
IREFST.             equ       4                   ; Internal Reference Status
CLKST1.             equ       3                   ; Clock Mode Status
CLKST0.             equ       2
OSCINIT.            equ       1                   ; OSC Initialization
FTRIM.              equ       0                   ; ICS Fine Trim

DRST1_              equ       1<DRST1.
DRST0_              equ       1<DRST0.
DRS1_               equ       1<DRS1.
DRS0_               equ       1<DRS0.
DMX32_              equ       1<DMX32.
IREFST_             equ       1<IREFST.
CLKST1_             equ       1<CLKST1.
CLKST0_             equ       1<CLKST0.
OSCINIT_            equ       1<OSCINIT.
FTRIM_              equ       1<FTRIM.

;-------------------------------------------------------------------------------
; Inter-Integrated Circuit (S08IICV2)
;-------------------------------------------------------------------------------

; IIC Control Register (IICxC1)

IICEN.              equ       7                   ; IIC Enable
IICIE.              equ       6                   ; IIC Interrupt Enable
MST.                equ       5                   ; Master Mode Select
TX.                 equ       4                   ; Transmit Mode Select
TXAK.               equ       3                   ; Transmit Acknowledge Enable
RSTA.               equ       2                   ; Repeat START

IICEN_              equ       1<IICEN.
IICIE_              equ       1<IICIE.
MST_                equ       1<MST.
TX_                 equ       1<TX.
TXAK_               equ       1<TXAK.
RSTA_               equ       1<RSTA.

; IIC Status Register (IICxS)

TCF.                equ       7                   ; Transfer Complete Flag
IIAS.               equ       6                   ; Addressed as slave
BUSY.               equ       5                   ; Bus Busy
ARBL.               equ       4                   ; Arbitration Lost
SRW.                equ       2                   ; Slave Read/Write
IICIF.              equ       1                   ; IIC Interrupt Flag
RXAK.               equ       0                   ; Receive Acknowledge

TCF_                equ       1<TCF.
IIAS_               equ       1<IIAS.
BUSY_               equ       1<BUSY.
ARBL_               equ       1<ARBL.
SRW_                equ       1<SRW.
IICIF_              equ       1<IICIF.
RXAK_               equ       1<RXAK.

; IIC Control Register 2 (IICxC2)

GCAEN.              equ       7                   ; General Call Address Enable
ADEXT.              equ       6                   ; Address Extension
AD10.               equ       2                   ; Slave Address (bits 10..8)
AD9.                equ       1
AD8.                equ       0

GCAEN_              equ       1<GCAEN.
ADEXT_              equ       1<ADEXT.
AD10_               equ       1<AD10.
AD9_                equ       1<AD9.
AD8_                equ       1<AD8.

;-------------------------------------------------------------------------------
; Real-Time Counter (S08RTCV1)
;-------------------------------------------------------------------------------

; RTC Status and Control Register (RTCSC)

RTIF.               equ       7                   ; Real-Time Interrupt Flag
RTCLKS1.            equ       6                   ; Real-Time Clock Source Select
RTCLKS0.            equ       5
RTIE.               equ       4                   ; Real-Time Interrupt Enable
RTCPS3.             equ       3                   ; Real-Time Clock Prescaler Select
RTCPS2.             equ       2
RTCPS1.             equ       1
RTCPS0.             equ       0

RTIF_               equ       1<RTIF.
RTCLKS1_            equ       1<RTCLKS1.
RTCLKS0_            equ       1<RTCLKS0.
RTIE_               equ       1<RTIE.
RTCPS3_             equ       1<RTCPS3.
RTCPS2_             equ       1<RTCPS2.
RTCPS1_             equ       1<RTCPS1.
RTCPS0_             equ       1<RTCPS0.

;-------------------------------------------------------------------------------
; Serial Communications Interface (S08SCIV4)
;-------------------------------------------------------------------------------

; SCI Baud Rate Registers (SCIxBDH, SCIxBDL)

LBKDIE.             equ       7                   ; LIN Break Detect Interrupt Enable (for LBKDIF)
RXEDGIE.            equ       6                   ; RxD Input Active Edge Interrupt Enable (for RXEDGIF)

LBKDIE_             equ       1<LBKDIE.
RXEDGIE_            equ       1<RXEDGIE.

; SCI Control Register 1 (SCIxC1)

LOOPS.              equ       7                   ; Loop Mode Select
SCISWAI.            equ       6                   ; SCI Stops in Wait Mode
RSRC.               equ       5                   ; Receiver Source Select
M.                  equ       4                   ; 9-Bit Mode Select
WAKE.               equ       3                   ; Receiver Wakeup Method Select
ILT.                equ       2                   ; Idle Line Type Select
PE.                 equ       1                   ; Parity Enable
PT.                 equ       0                   ; Parity Type

LOOPS_              equ       1<LOOPS.
SCISWAI_            equ       1<SCISWAI.
RSRC_               equ       1<RSRC.
M_                  equ       1<M.
WAKE_               equ       1<WAKE.
ILT_                equ       1<ILT.
PE_                 equ       1<PE.
PT_                 equ       1<PT.

; SCI Control Register 2 (SCIxC2)

TIE.                equ       7                   ; Transmit Interrupt Enable (for TDRE)
TCIE.               equ       6                   ; Transmission Complete Interrupt Enable (for TC)
RIE.                equ       5                   ; Receiver Interrupt Enable (for RDRF)
ILIE.               equ       4                   ; Idle Line Interrupt Enable (for IDLE)
TE.                 equ       3                   ; Transmitter Enable
RE.                 equ       2                   ; Receiver Enable
RWU.                equ       1                   ; Receiver Wakeup Control
SBK.                equ       0                   ; Send Break

TIE_                equ       1<TIE.
TCIE_               equ       1<TCIE.
RIE_                equ       1<RIE.
ILIE_               equ       1<ILIE.
TE_                 equ       1<TE.
RE_                 equ       1<RE.
RWU_                equ       1<RWU.
SBK_                equ       1<SBK.

; SCI Status Register 1 (SCIxS1)

TDRE.               equ       7                   ; Transmit Data Register Empty
TC.                 equ       6                   ; Transmission Complete Flag
RDRF.               equ       5                   ; Receive Data Register Full Flag
IDLE.               equ       4                   ; Idle Line Flag
OR.                 equ       3                   ; Receiver Overrun Flag
NF.                 equ       2                   ; Noise Flag
FE.                 equ       1                   ; Framing Error Flag
PF.                 equ       0                   ; Parity Errot Flag

TDRE_               equ       1<TDRE.
TC_                 equ       1<TC.
RDRF_               equ       1<RDRF.
IDLE_               equ       1<IDLE.
OR_                 equ       1<OR.
NF_                 equ       1<NF.
FE_                 equ       1<FE.
PF_                 equ       1<PF.

; SCI Status Register 2 (SCIxS2)

LBKDIF.             equ       7                   ; LIN Break Detect Interrupt Flag
RXEDGIF.            equ       6                   ; RxD Pin Active Edge Interrupt Flag
RXINV.              equ       4                   ; Receive Data Inversion
RWUID.              equ       3                   ; Receive Wakeup Idle Detect
BRK13.              equ       2                   ; Break Character Generation Length
LBKDE.              equ       1                   ; LIN Break Detection Enable
RAF.                equ       0                   ; Receiver Active Flag

LBKDIF_             equ       1<LBKDIF.
RXEDGIF_            equ       1<RXEDGIF.
RXINV_              equ       1<RXINV.
RWUID_              equ       1<RWUID.
BRK13_              equ       1<BRK13.
LBKDE_              equ       1<LBKDE.
RAF_                equ       1<RAF.

; SCI Control Register 3 (SCIxC3)

R8.                 equ       7                   ; Ninth Data Bit for Receiver
T8.                 equ       6                   ; Ninth Data Bit for Transmitter
TXDIR.              equ       5                   ; TxD Pin Direction in Single-Wire Mode
TXINV.              equ       4                   ; Transmit Data Inversion
ORIE.               equ       3                   ; Overrun Interrupt Enable
NEIE.               equ       2                   ; Noise Error Interrupt Enable
FEIE.               equ       1                   ; Framing Error Interrupt Enable
PEIE.               equ       0                   ; Parity Error Interrupt Enable

R8_                 equ       1<R8.
T8_                 equ       1<T8.
TXDIR_              equ       1<TXDIR.
TXINV_              equ       1<TXINV.
ORIE_               equ       1<ORIE.
NEIE_               equ       1<NEIE.
FEIE_               equ       1<FEIE.
PEIE_               equ       1<PEIE.

;-------------------------------------------------------------------------------
; Serial Peripheral Interface (S08SPIV3)
;-------------------------------------------------------------------------------

; SPI Control Register 1 (SPIxC1)

SPIE.               equ       7                   ; SPI Interrupt Enable (for SPRF and MODF)
SPE.                equ       6                   ; SPI System Enable
SPTIE.              equ       5                   ; SPI Transmit Interrupt Enable
MSTR.               equ       4                   ; Master/Slave Mode Select
CPOL.               equ       3                   ; Clock Polarity
CPHA.               equ       2                   ; Clock Phase
SSOE.               equ       1                   ; Slave Select Output Enable
LSBFE.              equ       0                   ; LSB First (Shifter Direction)

SPIE_               equ       1<SPIE.
SPE_                equ       1<SPE.
SPTIE_              equ       1<SPTIE.
MSTR_               equ       1<MSTR.
CPOL_               equ       1<CPOL.
CPHA_               equ       1<CPHA.
SSOE_               equ       1<SSOE.
LSBFE_              equ       1<LSBFE.

; SPI Control Register 2 (SPIxC2)

MODFEN.             equ       4                   ; Master Mode-Fault Function Enable
BIDIROE.            equ       3                   ; Bidirectional mode Output Enable
SPISWAI.            equ       1                   ; SPI Stop in Wait Mode
SPC0.               equ       0                   ; SPI Pin Control 0

MODFEN_             equ       1<MODFEN.
BIDIROE_            equ       1<BIDIROE.
SPISWAI_            equ       1<SPISWAI.
SPC0_               equ       1<SPC0.

; SPI Status Register (SPIxS)

SPRF.               equ       7                   ; SPI Read Buffer Full Flag
SPTEF.              equ       5                   ; SPI Transmit Buffer Empty Flag
MODF.               equ       4                   ; Master Mode Fault Flag

SPRF_               equ       1<SPRF.
SPTEF_              equ       1<SPTEF.
MODF_               equ       1<MODF.

;-------------------------------------------------------------------------------
; Timer/Pulse-Width Modulator (S08TPMV3)
;-------------------------------------------------------------------------------

; TPM Status and Control Register (TPMxSC)

TOF.                equ       7                   ; Timer Overflow Flag
TOIE.               equ       6                   ; Timer Overflow Interrupt Enable
CPWMS.              equ       5                   ; Center-aligned PWM Select
CLKSB.              equ       4                   ; Clock Source Select B
CLKSA.              equ       3                   ; Clock Source Select A
PS2.                equ       2                   ; Prescale factor Select
PS1.                equ       1
PS0.                equ       0

TOF_                equ       1<TOF.
TOIE_               equ       1<TOIE.
CPWMS_              equ       1<CPWMS.
CLKSB_              equ       1<CLKSB.
CLKSA_              equ       1<CLKSA.
PS2_                equ       1<PS2.
PS1_                equ       1<PS1.
PS0_                equ       1<PS0.

; TPM Channel n Status and Control Register (TPMxCnSC)

CHnF.               equ       7                   ; Channel n Flag
CHnIE.              equ       6                   ; Channel n Interrupt Enable
MSnB.               equ       5                   ; Mode Select B for TPM Channel n
MSnA.               equ       4                   ; Mode Select A for TPM Channel n
ELSnB.              equ       3                   ; Edge/Level Select Bits
ELSnA.              equ       2

CHnF_               equ       1<CHnF.
CHnIE_              equ       1<CHnIE.
MSnB_               equ       1<MSnB.
MSnA_               equ       1<MSnA.
ELSnB_              equ       1<ELSnB.
ELSnA_              equ       1<ELSnA.

;-------------------------------------------------------------------------------
; Background Debug Controller (BDC)
;-------------------------------------------------------------------------------

; BDC Status and Control Register (BDCSCR)

ENBDM.              equ       7                   ; Enable BDM (Permit Active Background Mode)
BDMACT.             equ       6                   ; Background Mode Active Status
BKPTEN.             equ       5                   ; BDC Breakpoint Enable
FTS.                equ       4                   ; Force/Tag Select
CLKSW.              equ       3                   ; Select Source for BDC Communications Clock
WS.                 equ       2                   ; Wait or Stop Status
WSF.                equ       1                   ; Wait or Stop Failure Status
DVF.                equ       0                   ; Data Valid Failure Status

ENBDM_              equ       1<ENBDM.
BDMACT_             equ       1<BDMACT.
BKPTEN_             equ       1<BKPTEN.
FTS_                equ       1<FTS.
CLKSW_              equ       1<CLKSW.
WS_                 equ       1<WS.
WSF_                equ       1<WSF.
DVF_                equ       1<DVF.

; System Background Debug Force Reset Register (SBDFR)

BDFR.               equ       0                   ; Background Debug Force Reset

BDFR_               equ       1<BDFR.

; Debug Comparator A Extension Register (DBGCAX)

RWAEN.              equ       7                   ; Read/Write Comparator A Enable Bit
RWA.                equ       6                   ; Read/Write Comparator A Value Bit
PAGSEL.             equ       5                   ; Comparator A Page Select Bit
BIT16.              equ       0                   ; Comparator A Extended Address Bit-16 Compare Bit

RWAEN_              equ       1<RWAEN.
RWA_                equ       1<RWA.
PAGSEL_             equ       1<PAGSEL.
BIT16_              equ       1<BIT16.

; Debug Comparator B Extension Register (DBGCBX)

RWBEN.              equ       7                   ; Read/Write Comparator B Enable Bit
RWB.                equ       6                   ; Read/Write Comparator B Value Bit

RWBEN_              equ       1<RWBEN.
RWB_                equ       1<RWB.

; Debug Comparator C Extension Register (DBGCCX)

RWCEN.              equ       7                   ; Read/Write Comparator C Enable Bit
RWC.                equ       6                   ; Read/Write Comparator C Value Bit

RWCEN_              equ       1<RWCEN.
RWC_                equ       1<RWC.

; Debug FIFO Extended Information Register (DBGFX)

PPACC.              equ       7                   ; PPAGE Access Indicator Bit

PPACC_              equ       1<PPACC.

; Debug Control Register (DBGC)

DBGEN.              equ       7                   ; DBG Module Enable Bit
ARM.                equ       6                   ; Arm bit
TAG.                equ       5                   ; Tar or Force Bit
BRKEN.              equ       4                   ; Break Enable Bit
LOOP1.              equ       0                   ; Select LOOP1 Capture Mode

DBGEN_              equ       1<DBGEN.
ARM_                equ       1<ARM.
TAG_                equ       1<TAG.
BRKEN_              equ       1<BRKEN.
LOOP1_              equ       1<LOOP1.

; Debug Trigger Register (DBGT)

TRGSEL.             equ       7                   ; Trigger Selection Bit
BEGIN.              equ       6                   ; Begin/End Trigger Bit
TRG3.               equ       3                   ; Trigger Mode Bits
TRG2.               equ       2
TRG1.               equ       1
TRG0.               equ       0

TRGSEL_             equ       1<TRGSEL.
BEGIN_              equ       1<BEGIN.
TRG3_               equ       1<TRG3.
TRG2_               equ       1<TRG2.
TRG1_               equ       1<TRG1.
TRG0_               equ       1<TRG0.

; Debug Status Register (DBGS)

AF.                 equ       7                   ; Trigger A Match Bit
BF.                 equ       6                   ; Trigger B Match Bit
CF.                 equ       5                   ; Trigger C Match Bit
ARMF.               equ       0                   ; Arm Flag Bit

AF_                 equ       1<AF.
BF_                 equ       1<BF.
CF_                 equ       1<CF.
ARMF_               equ       1<ARMF.

;*******************************************************************************
; Command codes for flash programming/erasure to be used with FCMD register
;*******************************************************************************

Blank_              equ       $05                 ; Blank Check command
ByteProg_           equ       $20                 ; Byte Program command
BurstProg_          equ       $25                 ; Burst Program command
PageErase_          equ       $40                 ; Page Erase command
MassErase_          equ       $41                 ; Mass Erase command

; **** Flash non-volatile register images **************************************

NVFTRIM             equ       $FFAE,1             ; NV FTRIM
NVICSTRM            equ       $FFAF,1             ; NV ICS Trim

NVBACKKEY           equ       $FFB0,8             ; 8-byte backdoor comparison key ($FFB0..$FFB7)

; Following 2 registers transfered from flash to working regs at reset

NVPROT              equ       $FFBD,1             ; NV flash protection byte
                                                  ; NVPROT transfers to FPROT on reset
NVOPT               equ       $FFBF,1             ; NV flash options byte
                                                  ; NVFEOPT transfers to FOPT on reset
;*******************************************************************************

TEMPERATURE_CHANNEL equ       26                  ;Channel for internal temperature
BANDGAP_CHANNEL     equ       27                  ;Channel for internal bandgap
BANDGAP_VOLTAGE     def       1170                ;typical bandgap voltage in mV

FLASH_PAGE_SIZE     equ       512                 ; minimum that must be erased at once
?SS                 equ       FLASH_PAGE_SIZE*2   ; Sector Size (minimum protected)

          #if FLASH_PAGE_SIZE <> 512
                    #Error    FLASH_PAGE_SIZE should be fixed at 512
          #endif

FLASH_DATA_SIZE     def       0                   ; default: no runtime flash storage
FLASH_DATA_SIZE     align     ?SS                 ; must be a multiple of Sector Size

                    #temp     $FFC0               ; start of fixed vectors
          #ifdef BOOT
VECTORS             def       BOOTROM+:temp&$FFFF
          #endif
VECTORS             def       :temp

          #ifdef BOOTROM
RVECTORS            set       BOOTROM+:temp&$FFFF           ; start of redirected vectors
                    #temp     $10000-BOOTROM/?SS
?NVPROT_MASK        equ       127-:temp<1|1                 ; using current BOOTROM
          #endif

                    #temp     FLASH_DATA_SIZE/?SS           ; minimum flash storage
          #if :temp = 128
?NVPROT_MASK        def       0
          #endif
?NVPROT_MASK        def       127-:temp<1|1

TRUE_ROM            equ       $4000               ; start(!) of 128K paged flash (do NOT use $2080-$3FFF which is also PPAGE 0)

EEPROM              def       TRUE_ROM
EEPROM_END          def       FLASH_DATA_SIZE+EEPROM-1

#ifdef BOOTROM
 #if EEPROM_END >= BOOTROM
                    #Error    FLASH_DATA_SIZE ({FLASH_DATA_SIZE}) is too large
 #endif
#endif

ROM                 def       EEPROM_END+1
ROM_END             def       :PAGE_START-1       ; end of pre-window flash

XROM                def       :PAGE_END+1
XROM_END            def       $FF9F               ; end of all flash (before NV registers and fixed vectors)

#ifdef BOOT&BOOTROM
XROM_END            set       BOOTROM-1
#endif

#if EEPROM_END <= HighRegs_End
ROM                 set       HighRegs_End+1
#endif

SERIAL_NUMBER       equ       $FFA0               ; start of optional S/N (FFA0-FFAD)

RAM                 equ       $0080               ; start of 8KB fragmented RAM
RAM_END             equ       HighRegs-1          ; last RAM location

XRAM                equ       HighRegs_End+1
XRAM_END            equ       $207F

#ifdef BOOTRAM_END
RAM                 set       BOOTRAM_END         ; start of 8KB fragmented RAM
#endif

#ifdef BOOTXRAM_END
XRAM                set       BOOTXRAM_END
#endif

FLASH_START         equ       XRAM_END+1
FLASH_END           equ       XROM_END

          #ifdef BOOTROM
FLASH_END           set       BOOTROM-1
          #endif

#ifndef MHZ
  #ifndef KHZ
HZ                  def       16777216            ;Cyclone 32768*512
  #endif
#endif

;-------------------------------------------------------------------------------
; Vectors
;-------------------------------------------------------------------------------

                    #temp     VECTORS

Vtpm3ovf            next      :temp,2             ; TPM3 overflow
Vtpm3ch5            next      :temp,2             ; TPM3 Channel 5
Vtpm3ch4            next      :temp,2             ; TPM3 Channel 4
Vtpm3ch3            next      :temp,2             ; TPM3 Channel 3
Vtpm3ch2            next      :temp,2             ; TPM3 Channel 2
Vtpm3ch1            next      :temp,2             ; TPM3 Channel 1
Vtpm3ch0            next      :temp,2             ; TPM3 Channel 0
Vrtc                next      :temp,2             ; Real-Time Clock
Vsci2tx             next      :temp,2             ; SCI2 transmit vector
Vsci2rx             next      :temp,2             ; SCI2 receive vector
Vsci2err            next      :temp,2             ; SCI2 error vector
Vacmpx              next      :temp,2             ; ACMP vector
Vadc                next      :temp,2             ; A/D vector
Vkeyboard           next      :temp,2             ; Keyboard vector
Viicx               next      :temp,2             ; IIC vector
Vsci1tx             next      :temp,2             ; SCI1 transmit vector
Vsci1rx             next      :temp,2             ; SCI1 receive vector
Vsci1err            next      :temp,2             ; SCI1 error vector
Vspi1               next      :temp,2             ; SPI1 vector
Vspi2               next      :temp,2             ; SPI2 vector
Vtpm2ovf            next      :temp,2             ; TPM2 overflow
Vtpm2ch2            next      :temp,2             ; TPM2 Channel 2
Vtpm2ch1            next      :temp,2             ; TPM2 Channel 1
Vtpm2ch0            next      :temp,2             ; TPM2 Channel 0
Vtpm1ovf            next      :temp,2             ; TPM1 overflow
Vtpm1ch2            next      :temp,2             ; TPM1 Channel 2
Vtpm1ch1            next      :temp,2             ; TPM1 Channel 1
Vtpm1ch0            next      :temp,2             ; TPM1 Channel 0
Vlvd                next      :temp,2             ; Low voltage detect
Virq                next      :temp,2             ; IRQ vector
Vswi                next      :temp,2             ; SWI vector
Vreset              next      :temp,2             ; Reset vector

Vtpmovf             equ       Vtpm1ovf,2          ; TPM1 overflow (alias)
Vtpmch2             equ       Vtpm1ch2,2          ; TPM1 Channel 2 (alias)
Vtpmch1             equ       Vtpm1ch1,2          ; TPM1 Channel 1 (alias)
Vtpmch0             equ       Vtpm1ch0,2          ; TPM1 Channel 0 (alias)

RVECTORS            def       EEPROM_END+VECTORS&$FFFF  ; start of redirected vectors

;-------------------------------------------------------------------------------
                    #Uses     common.inc
;-------------------------------------------------------------------------------

;----+-------+----------------------+------------+------------------------
;DRS | DMX32 | Reference range      | FLL factor | DCO range
;----+-------+----------------------+------------+------------------------
;00  |   0   | 31.25 - 39.0625 kHz  |     512    | 16 - 20 MHz
;00  |   1   | 32.768 kHz           |     608    | 19.92 MHz
;01  |   0   | 31.25 - 39.0625 kHz  |    1024    | 32 - 40 MHz
;01  |   1   | 32.768 kHz           |    1216    | 39.85 MHz
;10  |   0   | 31.25 - 39.0625 kHz  |    1536    | 48 - 60 MHz
;10  |   1   | 32.768 kHz           |    1824    | 59.77 MHz
;11  | Reserved

?                   macro     FLL_FACTOR,DRS,DMX(32)
                    mreq      1,2,3:FLL_FACTOR,DRS,DMX(32)
          #if FLL_FACTOR = ~1~
DRS_                equ       ~2~<DRS0.
DMX_                equ       ~3~<DMX32.
                    #Message  FLL_FACTOR = {FLL_FACTOR}, DRS_ = ~2~ ({DRS_}), DMX_ = ~3~ ({DMX_})
          #endif
                    endm

                    @?         512,0,0
                    @?         608,0,1
                    @?        1024,1,0
                    @?        1216,1,1
                    @?        1536,2,0
                    @?        1824,2,1

;*******************************************************************************

;                   @pin      SPI_SS,PORTE,3      ; SPI /SS port
;                   @pin      SPI2_SS,PORTD,3     ; SPI /SS port

                    #EEPROM
                    org       EEPROM

                    #DATA


#ifndef OS8PRELOADED
          #ifndef BOOT
                    org       NVPROT              ; NV flash protection byte
                    fcb       ?NVPROT_MASK        ; NVPROT transfers to FPROT on reset
                    #Message  NVPROT: {?NVPROT_MASK>1(h)} means {128+{?NVPROT_MASK>1-127(h)}} KB available to user

          #ifndef NVOPT_VALUE
                    #Message  Using default NVOPT_VALUE (no vector redirection)
          #endif

NVOPT_VALUE         def       %10000010           ; NVFEOPT transfers to FOPT on reset
                             ; ||||||++---------- SEC00 \ 00:secure  10:unsecure
                             ; ||||||++---------- SEC01 / 01:secure  11:secure
                             ; ||++++------------ Not Used (Always 0)
                             ; ++---------------- KEYEN - Backdoor key mechanism enable

                    org       NVOPT               ; NV flash options byte
                    fcb       NVOPT_VALUE         ; NVFEOPT transfers to FOPT on reset
          #endif
#endif
;                   org       NVICSTRIM           ; NV ICS Trim Setting
;                   fcb       ??                  ; ICG trim value measured during factory test. User software optionally
;                                                 ; copies to ICGTRM during initialization.
                    #VECTORS
                    org       VECTORS

?                   macro
                    #SEG{:loop-1}
                    org       :PAGE_START
                    mtop      8
                    endm

                    @?
          #ifmmu
PPAGE0              equ       $80<16+:PAGE_START  ;$80 instead of $00 on purpose (equivalent but unambiguous)
PPAGE1              equ       $01<16+:PAGE_START
PPAGE2              equ       $02<16+:PAGE_START
PPAGE3              equ       $03<16+:PAGE_START
PPAGE4              equ       $04<16+:PAGE_START
PPAGE5              equ       $05<16+:PAGE_START
PPAGE6              equ       $06<16+:PAGE_START
PPAGE7              equ       $07<16+:PAGE_START

PPAGE_SIZE          equ       :PAGE_END-:PAGE_START+1

?                   macro     Page
                    mswap     1,:loop
                    #SEG~1~
                    org       PPAGE~1~
                    #MEMORY   PPAGE~1~  PPAGE~1~+PPAGE_SIZE-1
                    mtop      :n
                    endm

                    @?        0,2,4,5,6,7         ;define memory for PPAGEs
          #endif
                    #XRAM
                    org       XRAM

                    #RAM
                    org       RAM

                    #XROM
                    org       XROM

                    #ROM
                    org       ROM

                    #MEMORY   ROM       ROM_END
          #ifndef OS8PRELOADED
                    #MEMORY   XROM      XROM_END
          #endif
                    #MEMORY   NVBACKKEY NVBACKKEY+7
                    #MEMORY   NVPROT
                    #MEMORY   NVOPT
                    #MEMORY   VECTORS   VECTORS|$00FF

          #ifnz FLASH_DATA_SIZE
                    #MEMORY   EEPROM EEPROM_END
          #endif

          #ifdef RVECTORS
                    #MEMORY   RVECTORS  RVECTORS|$00FF
          #endif