; FREEWARE, Copyright (c) Tony G. Papadimitriou <tonyp@acm.org>

                    #Uses     macros.inc
                    #Message  *********************
                    #Message  * Target: MC9S08SH8 *
                    #Message  *********************

                    #NoMMU                        ;MMU not available
#ifdef BOOT
                    #Message  TBoot pre-loaded
  #ifexists tboot.exp
                    #Uses     tboot.exp
                    #Uses     tboot/tboot32.exp


_SH_                def       8
_SH8_               def       *

;* Author: Tony Papadimitriou - <tonyp@acm.org>
;*         Jim Sibigtroth - Motorola TSPG (Original version)
;* Description: Register and bit name definitions for 9S08SH8
;* Documentation: 9S08SH8 family Data Sheet for register and bit explanations
;* HCS08 Family Reference Manual (HCS08RM1/D) appendix B for explanation of
;* equate files
;* Modified by <tonyp@acm.org> as follows:
;* 1. All bit names for use with BSET/BCLR/BRSET/BRCLR end with a dot (.)
;* 2. All bit names for use as masks end with an underscore (_)
;* 3. ASM8's segments RAM, ROM, XROM, SEG9 (OS8), EEPROM and VECTORS
;*    initialized with appropriate values for immediate use.
;* 4. The assembly-time symbol FLASH_DATA_SIZE optionally defines the protected Flash
;*    as the difference between total flash and FLASH_DATA_SIZE
;*    Based on MC9S08SH8's architecture, FLASH_DATA_SIZE can only take specific
;*    values.  An invalid value will cause an informative assembler error message.
;* 5. ASM8's #MEMORY directive used to define actual Flash space for user code/data
;* Include Files: COMMON.INC
;* Assembler:  ASM8 v9.65+ by Tony G. Papadimitriou <tonyp@acm.org>
;* Revision History: not yet released
;* Rev #     Date      Who     Comments
;* -----  -----------  ------  -------------------------------------------------
;*  1.0    24-Nov-13   T-Pap   Release version for 9S08SH8

; **** Memory Map and Interrupt Vectors ****************************************

HighRegs            equ       $1800               ; start of high page registers
HighRegs_End        equ       $185F               ; end of high page registers

; **** Input/Output (I/O) Ports ************************************************

PORTA               equ       $00,1               ;Port A Data Register; 0x00000000 ***
DDRA                equ       $01,1               ;Port A Data Direction Register; 0x00000001 ***
PORTB               equ       $02,1               ;Port B Data Register; 0x00000002 ***
DDRB                equ       $03,1               ;Port B Data Direction Register; 0x00000003 ***
PORTC               equ       $04,1               ;Port C Data Register; 0x00000004 ***
DDRC                equ       $05,1               ;Port C Data Direction Register; 0x00000005 ***
ACMPSC              equ       $0E,1               ;ACMP Status and Control Register; 0x0000000E ***

ADCSC1              equ       $10,1               ;Status and Control Register 1; 0x00000010 ***
ADCSC2              equ       $11,1               ;Status and Control Register 2; 0x00000011 ***
ADCR                equ       $12,2               ;Data Result Register
ADCRH               equ       $12,1               ;Data Result High Register
ADCRL               equ       $13,1               ;Data Result Low Register

ADCCV               equ       $14,2               ;Compare Value Register
ADCCVH              equ       $14,1               ;Compare Value High Register
ADCCVL              equ       $15,1               ;Compare Value Low Register

ADCCFG              equ       $16,1               ;Configuration Register

APCTL1              equ       $17,1               ;Pin Control 1 Register
APCTL2              equ       $18,1               ;Pin Control 2 Register

IRQSC               equ       $1A,1               ;Interrupt request status and control register

MTIMSC              equ       $1C,1               ;MTIM Clock Configuration Register

MTIMCLK             equ       $1D,1               ;MTIM Clock Configuration Register

MTIMCNT             equ       $1E,1               ;MTIM Counter Register
MTIMMOD             equ       $1F,1               ;MTIM Modulo Register

TPM1SC              equ       $20,1               ;TPM1 Status and Control Register

TPM1CNT             equ       $21,2               ;TPM1 Timer Counter Register
TPM1CNTH            equ       $21,1               ;TPM1 Timer Counter Register High
TPM1CNTL            equ       $22,1               ;TPM1 Timer Counter Register Low
TPM1MOD             equ       $23,2               ;TPM1 Timer Counter Modulo Register
TPM1MODH            equ       $23,1               ;TPM1 Timer Counter Modulo Register High
TPM1MODL            equ       $24,1               ;TPM1 Timer Counter Modulo Register Low
TPM1C0SC            equ       $25,1               ;TPM1 Timer Channel 0 Status and Control Register

TPM1C0V             equ       $26,2               ;TPM1 Timer Channel 0 Value Register
TPM1C0VH            equ       $26,1               ;TPM1 Timer Channel 0 Value Register High
TPM1C0VL            equ       $27,1               ;TPM1 Timer Channel 0 Value Register Low
TPM1C1SC            equ       $28,1               ;TPM1 Timer Channel 1 Status and Control Register

TPM1C1V             equ       $29,2               ;TPM1 Timer Channel 1 Value Register
TPM1C1VH            equ       $29,1               ;TPM1 Timer Channel 1 Value Register High
TPM1C1VL            equ       $2A,1               ;TPM1 Timer Channel 1 Value Register Low
SCIBD               equ       $38,2               ;SCI Baud Rate Register
SCIBDH              equ       $38,1               ;SCI Baud Rate Register High
SCIBDL              equ       $39,1               ;SCI Baud Rate Register Low
SCIC1               equ       $3A,1               ;SCI Control Register 1
SCIC2               equ       $3B,1               ;SCI Control Register 2
SCIS1               equ       $3C,1               ;SCI Status Register 1
SCIS2               equ       $3D,1               ;SCI Status Register 2
SCIC3               equ       $3E,1               ;SCI Control Register 3
SCID                equ       $3F,1               ;SCI Data Register

ICSC1               equ       $48,1               ;ICS Control Register 1
ICSC2               equ       $49,1               ;ICS Control Register 2
ICSTRM              equ       $4A,1               ;ICS Trim Register
ICSSC               equ       $4B,1               ;ICS Status and Control Register

SPIC1               equ       $50,1               ;SPI Control Register 1
SPIC2               equ       $51,1               ;SPI Control Register 2
SPIBR               equ       $52,1               ;SPI Baud Rate Register
SPIS                equ       $53,1               ;SPI Status Register
SPID                equ       $55,1               ;SPI Data Register

IICA                equ       $58,1               ;IIC Address Register
IICF                equ       $59,1               ;IIC Frequency Divider Register
IICC1               equ       $5A,1               ;IIC Control Register 1
IICC                equ       $5A,1               ;IIC Control Register
IICS                equ       $5B,1               ;IIC Status Register
IICD                equ       $5C,1               ;IIC Data I/O Register
IICC2               equ       $5D,1               ;IIC Control Register 2

TPM2SC              equ       $60,1               ;TPM2 Status and Control Register
TPM2CNT             equ       $61,2               ;TPM2 Timer Counter Register
TPM2CNTH            equ       $61,1               ;TPM2 Timer Counter Register High
TPM2CNTL            equ       $62,1               ;TPM2 Timer Counter Register Low
TPM2MOD             equ       $63,2               ;TPM2 Timer Counter Modulo Register
TPM2MODH            equ       $63,1               ;TPM2 Timer Counter Modulo Register High
TPM2MODL            equ       $64,1               ;TPM2 Timer Counter Modulo Register Low
TPM2C0SC            equ       $65,1               ;TPM2 Timer Channel 0 Status and Control Register
TPM2C0V             equ       $66,2               ;TPM2 Timer Channel 0 Value Register
TPM2C0VH            equ       $66,1               ;TPM2 Timer Channel 0 Value Register High
TPM2C0VL            equ       $67,1               ;TPM2 Timer Channel 0 Value Register Low
TPM2C1SC            equ       $68,1               ;TPM2 Timer Channel 1 Status and Control Register
TPM2C1V             equ       $69,2               ;TPM2 Timer Channel 1 Value Register
TPM2C1VH            equ       $69,1               ;TPM2 Timer Channel 1 Value Register High
TPM2C1VL            equ       $6A,1               ;TPM2 Timer Channel 1 Value Register Low

RTCSC               equ       $6C,1               ;RTC Status and Control Register
RTCCNT              equ       $6D,1               ;RTC Counter Register
RTCMOD              equ       $6E,1               ;RTC Modulo Register

SRS                 equ       $1800,1             ;System Reset Status Register
COP                 equ       SRS,1               ;for "STA COP"

SBDFR               equ       $1801,1             ;System Background Debug Force Reset Register
SOPT1               equ       $1802,1             ;System Options Register 1
SOPT2               equ       $1803,1             ;System Options Register 2
SDID                equ       $1806,2             ;System Device Identification Register
SDIDH               equ       $1806,1             ;System Device Identification Register High
SDIDL               equ       $1807,1             ;System Device Identification Register Low

SPMSC1              equ       $1809,1             ;System Power Management Status and Control 1 Register
SPMSC2              equ       $180A,1             ;System Power Management Status and Control 2 Register

DBGCA               equ       $1810,2             ;Debug Comparator A Register
DBGCAH              equ       $1810,1             ;Debug Comparator A High Register
DBGCAL              equ       $1811,1             ;Debug Comparator A Low Register
DBGCB               equ       $1812,2             ;Debug Comparator B Register
DBGCBH              equ       $1812,1             ;Debug Comparator B High Register
DBGCBL              equ       $1813,1             ;Debug Comparator B Low Register
DBGF                equ       $1814,2             ;Debug FIFO Register
DBGFH               equ       $1814,1             ;Debug FIFO High Register
DBGFL               equ       $1815,1             ;Debug FIFO Low Register
DBGC                equ       $1816,1             ;Debug Control Register
DBGT                equ       $1817,1             ;Debug Trigger Register
DBGS                equ       $1818,1             ;Debug Status Register

FCDIV               equ       $1820,1             ;FLASH Clock Divider Register
FOPT                equ       $1821,1             ;FLASH Options Register
FCNFG               equ       $1823,1             ;FLASH Configuration Register
FPROT               equ       $1824,1             ;FLASH Protection Register
FSTAT               equ       $1825,1             ;Flash Status Register
FCMD                equ       $1826,1             ;FLASH Command Register

PTAPE               equ       $1840,1             ;Port A Pull Enable Register
PTASE               equ       $1841,1             ;Port A Slew Rate Enable Register
PTADS               equ       $1842,1             ;Port A Drive Strength Selection Register
PTASC               equ       $1844,1             ;Port A Interrupt Status and Control Register

PTAPS               equ       $1845,1             ;Port A Interrupt Pin Select Register
PTAES               equ       $1846,1             ;Port A Interrupt Edge Select Register
PTBPE               equ       $1848,1             ;Port B Pull Enable Register
PTBSE               equ       $1849,1             ;Port B Slew Rate Enable Register
PTBDS               equ       $184A,1             ;Port B Drive Strength Selection Register
PTBSC               equ       $184C,1             ;Port B Interrupt Status and Control Register

PTBPS               equ       $184D,1             ;Port B Interrupt Pin Select Register
PTBES               equ       $184E,1             ;Port B Interrupt Edge Select Register
PTCPE               equ       $1850,1             ;Port C Pull Enable Register
PTCSE               equ       $1851,1             ;Port C Slew Rate Enable Register
PTCDS               equ       $1852,1             ;Port C Drive Strength Selection Register
GNGC                equ       $1853,1             ;Ganged Output Drive Control Register

NVFTRIM             equ       $FFAE,1             ;Nonvolatile ICS Fine Trim
NVICSTRM            equ       $FFAF,1             ;Nonvolatile ICS Trim Register
NVBACKKEY           equ       $FFB0,8             ;Backdoor Comparison Key
NVPROT              equ       $FFBD,1             ;Nonvolatile FLASH Protection Register
NVOPT               equ       $FFBF,1             ;Nonvolatile Flash Options Register

; Bit numbers for use in BCLR, BSET, BRCLR, and BRSET

; ACMPx Status and Control Register (ACMPxSC)

ACME.               equ       7                   ; Analog Comparator Module Enable
ACBGS.              equ       6                   ; Analog Comparator Bandgap Select
ACF.                equ       5                   ; Analog Comparator Flag
ACIE.               equ       4                   ; Analog Comparator Interrupt Enable
ACO.                equ       3                   ; Analog Comparator Output
ACOPE.              equ       2                   ; Analog Comparator Output Pin Enable
ACMOD1.             equ       1                   ; Analog Comparator Mode
ACMOD0.             equ       0

ACME_               equ       1<ACME.
ACBGS_              equ       1<ACBGS.
ACF_                equ       1<ACF.
ACIE_               equ       1<ACIE.
ACO_                equ       1<ACO.
ACOPE_              equ       1<ACOPE.
ACMOD1_             equ       1<ACMOD1.
ACMOD0_             equ       1<ACMOD0.

; Status and Control Register 1 (ADCSC1)

COCO.               equ       7                   ; Conversion Complete Flag
AIEN.               equ       6                   ; Interrupt Enable
ADCO.               equ       5                   ; Continuous Conversion Enable

COCO_               equ       1<COCO.
AIEN_               equ       1<AIEN.
ADCO_               equ       1<ADCO.

; Status and Control Register 2 (ADCSC2)

ADACT.              equ       7                   ; Conversion Active
ADTRG.              equ       6                   ; Conversion Trigger Select
ACFE.               equ       5                   ; Compare Function Enable
ACFGT.              equ       4                   ; Compare Function Greater Than Enable

ADACT_              equ       1<ADACT.
ADTRG_              equ       1<ADTRG.
ACFE_               equ       1<ACFE.
ACFGT_              equ       1<ACFGT.

; Configuration Register (ADCCFG)

ADLPC.              equ       7                   ; Low Power Configuration
ADIV1.              equ       6                   ; Clock Divide Select
ADIV0.              equ       5
ADLSMP.             equ       4                   ; Long Sample Time Configuration
MODE1.              equ       3                   ; Conversion Mode Select
MODE0.              equ       2
ADICLK1.            equ       1                   ; Input Clock Select
ADICLK0.            equ       0

ADLPC_              equ       1<ADLPC.
ADIV1_              equ       1<ADIV1.
ADIV0_              equ       1<ADIV0.
ADLSMP_             equ       1<ADLSMP.
MODE1_              equ       1<MODE1.
MODE0_              equ       1<MODE0.
ADICLK1_            equ       1<ADICLK1.
ADICLK0_            equ       1<ADICLK0.

; IRQ Status and Control (IRQSC)

IRQPDD.             equ       6                   ; IRQ Pulldown Disable
IRQEDG.             equ       5                   ; IRQ Edge Select
IRQPE.              equ       4                   ; IRQ Pin Enable
IRQF.               equ       3                   ; IRQ Flag
IRQACK.             equ       2                   ; IRQ Acknowledge
IRQIE.              equ       1                   ; IRQ Interrupt Enable
IRQMOD.             equ       0                   ; IRQ Detection Mode

IRQPDD_             equ       1<IRQPDD.
IRQEDG_             equ       1<IRQEDG.
IRQPE_              equ       1<IRQPE.
IRQF_               equ       1<IRQF.
IRQACK_             equ       1<IRQACK.
IRQIE_              equ       1<IRQIE.
IRQMOD_             equ       1<IRQMOD.


TRST.               equ       5
TSTP.               equ       4

TRST_               equ       1<TRST.
TSTP_               equ       1<TSTP.

; Timer/Pulse-Width Modulator (S08TPMV3)

; TPM Status and Control Register (TPMxSC)

TOF.                equ       7                   ; Timer Overflow Flag
TOIE.               equ       6                   ; Timer Overflow Interrupt Enable
CPWMS.              equ       5                   ; Center-aligned PWM Select
CLKSB.              equ       4                   ; Clock Source Select B
CLKSA.              equ       3                   ; Clock Source Select A
PS2.                equ       2                   ; Prescale factor Select
PS1.                equ       1
PS0.                equ       0

TOF_                equ       1<TOF.
TOIE_               equ       1<TOIE.
CPWMS_              equ       1<CPWMS.
CLKSB_              equ       1<CLKSB.
CLKSA_              equ       1<CLKSA.
PS2_                equ       1<PS2.
PS1_                equ       1<PS1.
PS0_                equ       1<PS0.

; TPM Channel n Status and Control Register (TPMxCnSC)

CHnF.               equ       7                   ; Channel n Flag
CHnIE.              equ       6                   ; Channel n Interrupt Enable
MSnB.               equ       5                   ; Mode Select B for TPM Channel n
MSnA.               equ       4                   ; Mode Select A for TPM Channel n
ELSnB.              equ       3                   ; Edge/Level Select Bits
ELSnA.              equ       2

CHnF_               equ       1<CHnF.
CHnIE_              equ       1<CHnIE.
MSnB_               equ       1<MSnB.
MSnA_               equ       1<MSnA.
ELSnB_              equ       1<ELSnB.
ELSnA_              equ       1<ELSnA.

; Serial Communications Interface (S08SCIV4)

; SCI Baud Rate Registers (SCIxBDH, SCIxBDL)

LBKDIE.             equ       7                   ; LIN Break Detect Interrupt Enable (for LBKDIF)
RXEDGIE.            equ       6                   ; RxD Input Active Edge Interrupt Enable (for RXEDGIF)

LBKDIE_             equ       1<LBKDIE.
RXEDGIE_            equ       1<RXEDGIE.

; SCI Control Register 1 (SCIxC1)

LOOPS.              equ       7                   ; Loop Mode Select
SCISWAI.            equ       6                   ; SCI Stops in Wait Mode
RSRC.               equ       5                   ; Receiver Source Select
M.                  equ       4                   ; 9-Bit Mode Select
WAKE.               equ       3                   ; Receiver Wakeup Method Select
ILT.                equ       2                   ; Idle Line Type Select
PE.                 equ       1                   ; Parity Enable
PT.                 equ       0                   ; Parity Type

LOOPS_              equ       1<LOOPS.
SCISWAI_            equ       1<SCISWAI.
RSRC_               equ       1<RSRC.
M_                  equ       1<M.
WAKE_               equ       1<WAKE.
ILT_                equ       1<ILT.
PE_                 equ       1<PE.
PT_                 equ       1<PT.

; SCI Control Register 2 (SCIxC2)

TIE.                equ       7                   ; Transmit Interrupt Enable (for TDRE)
TCIE.               equ       6                   ; Transmission Complete Interrupt Enable (for TC)
RIE.                equ       5                   ; Receiver Interrupt Enable (for RDRF)
ILIE.               equ       4                   ; Idle Line Interrupt Enable (for IDLE)
TE.                 equ       3                   ; Transmitter Enable
RE.                 equ       2                   ; Receiver Enable
RWU.                equ       1                   ; Receiver Wakeup Control
SBK.                equ       0                   ; Send Break

TIE_                equ       1<TIE.
TCIE_               equ       1<TCIE.
RIE_                equ       1<RIE.
ILIE_               equ       1<ILIE.
TE_                 equ       1<TE.
RE_                 equ       1<RE.
RWU_                equ       1<RWU.
SBK_                equ       1<SBK.

; SCI Status Register 1 (SCIxS1)

TDRE.               equ       7                   ; Transmit Data Register Empty
TC.                 equ       6                   ; Transmission Complete Flag
RDRF.               equ       5                   ; Receive Data Register Full Flag
IDLE.               equ       4                   ; Idle Line Flag
OR.                 equ       3                   ; Receiver Overrun Flag
NF.                 equ       2                   ; Noise Flag
FE.                 equ       1                   ; Framing Error Flag
PF.                 equ       0                   ; Parity Errot Flag

TDRE_               equ       1<TDRE.
TC_                 equ       1<TC.
RDRF_               equ       1<RDRF.
IDLE_               equ       1<IDLE.
OR_                 equ       1<OR.
NF_                 equ       1<NF.
FE_                 equ       1<FE.
PF_                 equ       1<PF.

; SCI Status Register 2 (SCIxS2)

LBKDIF.             equ       7                   ; LIN Break Detect Interrupt Flag
RXEDGIF.            equ       6                   ; RxD Pin Active Edge Interrupt Flag
RXINV.              equ       4                   ; Receive Data Inversion
RWUID.              equ       3                   ; Receive Wakeup Idle Detect
BRK13.              equ       2                   ; Break Character Generation Length
LBKDE.              equ       1                   ; LIN Break Detection Enable
RAF.                equ       0                   ; Receiver Active Flag

LBKDIF_             equ       1<LBKDIF.
RXEDGIF_            equ       1<RXEDGIF.
RXINV_              equ       1<RXINV.
RWUID_              equ       1<RWUID.
BRK13_              equ       1<BRK13.
LBKDE_              equ       1<LBKDE.
RAF_                equ       1<RAF.

; SCI Control Register 3 (SCIxC3)

R8.                 equ       7                   ; Ninth Data Bit for Receiver
T8.                 equ       6                   ; Ninth Data Bit for Transmitter
TXDIR.              equ       5                   ; TxD Pin Direction in Single-Wire Mode
TXINV.              equ       4                   ; Transmit Data Inversion
ORIE.               equ       3                   ; Overrun Interrupt Enable
NEIE.               equ       2                   ; Noise Error Interrupt Enable
FEIE.               equ       1                   ; Framing Error Interrupt Enable
PEIE.               equ       0                   ; Parity Error Interrupt Enable

R8_                 equ       1<R8.
T8_                 equ       1<T8.
TXDIR_              equ       1<TXDIR.
TXINV_              equ       1<TXINV.
ORIE_               equ       1<ORIE.
NEIE_               equ       1<NEIE.
FEIE_               equ       1<FEIE.
PEIE_               equ       1<PEIE.

; Internal Clock Source (ICS)


CLKS1.              equ       7                   ; Clock Source Select
CLKS0.              equ       6
RDIV2.              equ       5                   ; Reference Divider
RDIV1.              equ       4
RDIV0.              equ       3
IREFS.              equ       2                   ; Internal Reference Select
IRCLKEN.            equ       1                   ; Internal Reference Clock Enable
IREFSTEN.           equ       0                   ; Internal Reference Stop Enable

CLKS1_              equ       1<CLKS1.
CLKS0_              equ       1<CLKS0.
RDIV2_              equ       1<RDIV2.
RDIV1_              equ       1<RDIV1.
RDIV0_              equ       1<RDIV0.
IREFS_              equ       1<IREFS.
IRCLKEN_            equ       1<IRCLKEN.
IREFSTEN_           equ       1<IREFSTEN.


BDIV1.              equ       7                   ; Bus Frequency Divider
BDIV0.              equ       6
RANGE_SEL.          equ       5                   ; Frequency Range Select
HGO.                equ       4                   ; High Gain Oscillator Select
LP.                 equ       3                   ; Low Power Select
EREFS.              equ       2                   ; External Reference Select
ERCLKEN.            equ       1                   ; External Reference Enable
EREFSTEN.           equ       0                   ; External Reference Stop Enable

BDIV1_              equ       1<BDIV1.
BDIV0_              equ       1<BDIV0.
RANGE_SEL_          equ       1<RANGE_SEL.
HGO_                equ       1<HGO.
LP_                 equ       1<LP.
EREFS_              equ       1<EREFS.
ERCLKEN_            equ       1<ERCLKEN.
EREFSTEN_           equ       1<EREFSTEN.


IREFST.             equ       4                   ; Internal Reference Status
CLKST1.             equ       3                   ; Clock Mode Status
CLKST0.             equ       2
OSCINIT.            equ       1                   ; OSC Initialization
FTRIM.              equ       0                   ; ICS Fine Trim

IREFST_             equ       1<IREFST.
CLKST1_             equ       1<CLKST1.
CLKST0_             equ       1<CLKST0.
OSCINIT_            equ       1<OSCINIT.
FTRIM_              equ       1<FTRIM.

; Serial Peripheral Interface (S08SPIV3)

; SPI Control Register 1 (SPIxC1)

SPIE.               equ       7                   ; SPI Interrupt Enable (for SPRF and MODF)
SPE.                equ       6                   ; SPI System Enable
SPTIE.              equ       5                   ; SPI Transmit Interrupt Enable
MSTR.               equ       4                   ; Master/Slave Mode Select
CPOL.               equ       3                   ; Clock Polarity
CPHA.               equ       2                   ; Clock Phase
SSOE.               equ       1                   ; Slave Select Output Enable
LSBFE.              equ       0                   ; LSB First (Shifter Direction)

SPIE_               equ       1<SPIE.
SPE_                equ       1<SPE.
SPTIE_              equ       1<SPTIE.
MSTR_               equ       1<MSTR.
CPOL_               equ       1<CPOL.
CPHA_               equ       1<CPHA.
SSOE_               equ       1<SSOE.
LSBFE_              equ       1<LSBFE.

; SPI Control Register 2 (SPIxC2)

MODFEN.             equ       4                   ; Master Mode-Fault Function Enable
BIDIROE.            equ       3                   ; Bidirectional mode Output Enable
SPISWAI.            equ       1                   ; SPI Stop in Wait Mode
SPC0.               equ       0                   ; SPI Pin Control 0

MODFEN_             equ       1<MODFEN.
BIDIROE_            equ       1<BIDIROE.
SPISWAI_            equ       1<SPISWAI.
SPC0_               equ       1<SPC0.

; SPI Status Register (SPIxS)

SPRF.               equ       7                   ; SPI Read Buffer Full Flag
SPTEF.              equ       5                   ; SPI Transmit Buffer Empty Flag
MODF.               equ       4                   ; Master Mode Fault Flag

SPRF_               equ       1<SPRF.
SPTEF_              equ       1<SPTEF.
MODF_               equ       1<MODF.

; Inter-Integrated Circuit (S08IICV2)

; IIC Control Register (IICxC1)

IICEN.              equ       7                   ; IIC Enable
IICIE.              equ       6                   ; IIC Interrupt Enable
MST.                equ       5                   ; Master Mode Select
TX.                 equ       4                   ; Transmit Mode Select
TXAK.               equ       3                   ; Transmit Acknowledge Enable
RSTA.               equ       2                   ; Repeat START

IICEN_              equ       1<IICEN.
IICIE_              equ       1<IICIE.
MST_                equ       1<MST.
TX_                 equ       1<TX.
TXAK_               equ       1<TXAK.
RSTA_               equ       1<RSTA.

; IIC Status Register (IICxS)

TCF.                equ       7                   ; Transfer Complete Flag
IIAS.               equ       6                   ; Addressed as slave
BUSY.               equ       5                   ; Bus Busy
ARBL.               equ       4                   ; Arbitration Lost
SRW.                equ       2                   ; Slave Read/Write
IICIF.              equ       1                   ; IIC Interrupt Flag
RXAK.               equ       0                   ; Receive Acknowledge

TCF_                equ       1<TCF.
IIAS_               equ       1<IIAS.
BUSY_               equ       1<BUSY.
ARBL_               equ       1<ARBL.
SRW_                equ       1<SRW.
IICIF_              equ       1<IICIF.
RXAK_               equ       1<RXAK.

; IIC Control Register 2 (IICxC2)

GCAEN.              equ       7                   ; General Call Address Enable
ADEXT.              equ       6                   ; Address Extension
AD10.               equ       2                   ; Slave Address (bits 10..8)
AD9.                equ       1
AD8.                equ       0

GCAEN_              equ       1<GCAEN.
ADEXT_              equ       1<ADEXT.
AD10_               equ       1<AD10.
AD9_                equ       1<AD9.
AD8_                equ       1<AD8.

; Real-Time Counter (S08RTCV1)

; RTC Status and Control Register (RTCSC)

RTIF.               equ       7                   ; Real-Time Interrupt Flag
RTCLKS1.            equ       6                   ; Real-Time Clock Source Select
RTCLKS0.            equ       5
RTIE.               equ       4                   ; Real-Time Interrupt Enable
RTCPS3.             equ       3                   ; Real-Time Clock Prescaler Select
RTCPS2.             equ       2
RTCPS1.             equ       1
RTCPS0.             equ       0

RTIF_               equ       1<RTIF.
RTCLKS1_            equ       1<RTCLKS1.
RTCLKS0_            equ       1<RTCLKS0.
RTIE_               equ       1<RTIE.
RTCPS3_             equ       1<RTCPS3.
RTCPS2_             equ       1<RTCPS2.
RTCPS1_             equ       1<RTCPS1.
RTCPS0_             equ       1<RTCPS0.

; System Reset Status Register (SRS)

POR.                equ       7                   ; Power-On Reset
PIN.                equ       6                   ; External Reset Pin
COP.                equ       5                   ; COP Watchdog
ILOP.               equ       4                   ; Illegal Opcode
ILAD.               equ       3                   ; Illegal Address
LVD.                equ       1                   ; Low Voltage Detect

POR_                equ       1<POR.
PIN_                equ       1<PIN.
COP_                equ       1<COP.
ILOP_               equ       1<ILOP.
ILAD_               equ       1<ILAD.
LVD_                equ       1<LVD.

; System Options Register 1 (SOPT1)

COPT1.              equ       7                   ; COP Watchdog Enable
COPT0.              equ       6                   ; COP Watchdog Timeout
STOPE.              equ       5                   ; Stop Mode Enable
IICPS.              equ       2                   ; IIC Pin Select
BKGDPE.             equ       1                   ; Background Debug Mode Pin Enable
RSTPE.              equ       0                   ; /RESET Pin Enable

COPT1_              equ       1<COPT1.
COPT0_              equ       1<COPT0.
STOPE_              equ       1<STOPE.
IICPS_              equ       1<IICPS.
BKGDPE_             equ       1<BKGDPE.
RSTPE_              equ       1<RSTPE.

; System Options Register 2 (SOPT2)

COPCLKS.            equ       7                   ; COP Watchdog Clock Select
COPW.               equ       6                   ; COP Windowed
ACIC.               equ       4                   ; Analog Comparator to Input Capture Enable
T1CH1PS.            equ       1                   ; TPM1CH1 Pin Select
T1CH0PS.            equ       0                   ; TPM1CH0 Pin Select

COPCLKS_            equ       1<COPCLKS.
COPW_               equ       1<COPW.
ACIC_               equ       1<ACIC.
T1CH1PS_            equ       1<T1CH1PS.
T1CH0PS_            equ       1<T1CH0PS.

; System Power Management Status and Control 1 Register (SPMSC1)

LVWF.               equ       7                   ; Low-Voltage Warning Flag
LVWACK.             equ       6                   ; Low-Voltage Warning Acknowledge
LVWIE.              equ       5                   ; Low-Voltage Warning Interrupt Enable
LVDRE.              equ       4                   ; Low-Voltage Detection Reset Enable
LVDSE.              equ       3                   ; Low-Voltage Detection Stop Enable
LVDE.               equ       2                   ; Low-Voltage Detection Enable
BGBE.               equ       0                   ; Bandgap Buffer Enable

LVWF_               equ       1<LVWF.
LVWACK_             equ       1<LVWACK.
LVWIE_              equ       1<LVWIE.
LVDRE_              equ       1<LVDRE.
LVDSE_              equ       1<LVDSE.
LVDE_               equ       1<LVDE.
BGBE_               equ       1<BGBE.

; System Power Management Status and Control 2 Register (SPMSC2)

LVDV.               equ       5                   ; Low-Voltage Voltage level
LVWV.               equ       4                   ; Low-Voltage Warning Voltage
PPDF.               equ       3                   ; Partial Power Down Flag
PPDACK.             equ       2                   ; Partial Power Down Acknowledge
PPDC.               equ       0                   ; Partial Power Down Control

LVDV_               equ       1<LVDV.
LVWV_               equ       1<LVWV.
PPDF_               equ       1<PPDF.
PPDACK_             equ       1<PPDACK.
PPDC_               equ       1<PPDC.

; Background Debug Controller (BDC)

; Debug Control Register (DBGC)

DBGEN.              equ       7                   ; DBG Module Enable Bit
ARM.                equ       6                   ; Arm bit
TAG.                equ       5                   ; Tar or Force Bit
BRKEN.              equ       4                   ; Break Enable Bit
RWA.                equ       3
RWAEN.              equ       2
RWB.                equ       1
RWBEN.              equ       0

DBGEN_              equ       1<DBGEN.
ARM_                equ       1<ARM.
TAG_                equ       1<TAG.
BRKEN_              equ       1<BRKEN.
RWA_                equ       1<RWA.
RWAEN_              equ       1<RWAEN.
RWB_                equ       1<RWB.

; Debug Trigger Register (DBGT)

TRGSEL.             equ       7                   ; Trigger Selection Bit
BEGIN.              equ       6                   ; Begin/End Trigger Bit
TRG3.               equ       3                   ; Trigger Mode Bits
TRG2.               equ       2
TRG1.               equ       1
TRG0.               equ       0

TRGSEL_             equ       1<TRGSEL.
BEGIN_              equ       1<BEGIN.
TRG3_               equ       1<TRG3.
TRG2_               equ       1<TRG2.
TRG1_               equ       1<TRG1.
TRG0_               equ       1<TRG0.

; Debug Status Register (DBGS)

AF.                 equ       7                   ; Trigger A Match Bit
BF.                 equ       6                   ; Trigger B Match Bit
ARMF.               equ       5                   ; Arm Flag Bit
CNT3.               equ       3
CNT2.               equ       2
CNT1.               equ       1
CNT0.               equ       0

AF_                 equ       1<AF.
BF_                 equ       1<BF.
ARMF_               equ       1<ARMF.
CNT3_               equ       1<CNT3.
CNT2_               equ       1<CNT2.
CNT1_               equ       1<CNT1.
CNT0_               equ       1<CNT0.

; BDC Status and Control Register (BDCSCR)

ENBDM.              equ       7                   ; Enable BDM (Permit Active Background Mode)
BDMACT.             equ       6                   ; Background Mode Active Status
BKPTEN.             equ       5                   ; BDC Breakpoint Enable
FTS.                equ       4                   ; Force/Tag Select
CLKSW.              equ       3                   ; Select Source for BDC Communications Clock
WS.                 equ       2                   ; Wait or Stop Status
WSF.                equ       1                   ; Wait or Stop Failure Status
DVF.                equ       0                   ; Data Valid Failure Status

ENBDM_              equ       1<ENBDM.
BDMACT_             equ       1<BDMACT.
BKPTEN_             equ       1<BKPTEN.
FTS_                equ       1<FTS.
CLKSW_              equ       1<CLKSW.
WS_                 equ       1<WS.
WSF_                equ       1<WSF.
DVF_                equ       1<DVF.

; Flash

; Flash Clock Divider Register (FCDIV)

DIVLD.              equ       7                   ; Clock Divider Load Control
PRDIV8.             equ       6                   ; Enable Prescaler by 8

DIVLD_              equ       1<DIVLD.
PRDIV8_             equ       1<PRDIV8.

; Flash Options Register (FOPT and NVOPT)

KEYEN.              equ       7                   ; Backdoor Key Security Enable
FNORED.             equ       6
SEC1.               equ       1                   ; Flash Security Bits
SEC0.               equ       0

KEYEN_              equ       1<KEYEN.
FNORED_             equ       1<FNORED.
SEC1_               equ       1<SEC1.
SEC0_               equ       1<SEC0.

; Flash Configuration Register (FCNFG)

KEYACC.             equ       5                   ; Enable Security Key Writing

KEYACC_             equ       1<KEYACC.

; Flash Protection Register (FPROT and NVPROT)

FPDIS.              equ       0                   ; Flash Protection Disable

FPDIS_              equ       1<FPDIS.

; Flash Status Register (FSTAT)

FCBEF.              equ       7                   ; Flash Command Buffer Empty Flag
FCCF.               equ       6                   ; Flash Command Complete Interrupt Flag
FPVIOL.             equ       5                   ; Flash Protection Violation Flag
FACCERR.            equ       4                   ; Flash Access Error Flag
FBLANK.             equ       2                   ; Flash Flag Indicating the Erase Verify Operation Status

FCBEF_              equ       1<FCBEF.
FCCF_               equ       1<FCCF.
FPVIOL_             equ       1<FPVIOL.
FACCERR_            equ       1<FACCERR.
FBLANK_             equ       1<FBLANK.

; Port A/B Interrupt Status and Control

PTAIF.              equ       3                   ;PORTA Interrupt Flag
PTAACK.             equ       2                   ;PORTA Interrupt Acknowledge
PTAIE.              equ       1                   ;PORTA Interrupt Enable
PTAMOD.             equ       0                   ;PORTA Detection Mode

PTAIF_              equ       1<PTAIF.
PTAACK_             equ       1<PTAACK.
PTAIE_              equ       1<PTAIE.
PTAMOD_             equ       1<PTAMOD.

PTBIF.              equ       3                   ;PORTB Interrupt Flag
PTBACK.             equ       2                   ;PORTB Interrupt Acknowledge
PTBIE.              equ       1                   ;PORTB Interrupt Enable
PTBMOD.             equ       0                   ;PORTB Detection Mode

PTBIF_              equ       1<PTBIF.
PTBACK_             equ       1<PTBACK.
PTBIE_              equ       1<PTBIE.
PTBMOD_             equ       1<PTBMOD.

; Ganged output

GNGEN.              equ       0              ; Ganged Output Drive Enable Bit

GNGEN_              equ       1<GNGEN.

; Command codes for flash programming/erasure to be used with FCMD register

Blank_              equ       $05                 ; Blank Check command
ByteProg_           equ       $20                 ; Byte Program command
BurstProg_          equ       $25                 ; Burst Program command
PageErase_          equ       $40                 ; Page Erase command
MassErase_          equ       $41                 ; Mass Erase command

; **** END OF ORIGINAL DEFINITIONS *********************************************

_9S08SH8_           def       *                   ;Tells us this INCLUDE has been used

TEMPERATURE_CHANNEL equ       26                  ;Channel for internal temperature
BANDGAP_CHANNEL     equ       27                  ;Channel for internal bandgap

FLASH_PAGE_SIZE     equ       512                 ; minimum that must be erased at once

          #if FLASH_PAGE_SIZE <> 512
                    #Error    FLASH_PAGE_SIZE should be fixed at 512

FLASH_DATA_SIZE     def       0                   ; default: no runtime flash storage

VECTORS             equ       $FFC0               ; start of fixed vectors

          #ifdef RVECTORS
VECTORS             set       RVECTORS

; Vectors
                    #temp     VECTORS
                    next      :temp,2
Vacmp               next      :temp,2
                    next      :temp,2*3
Vmtim               next      :temp,2
Vrtc                next      :temp,2
Viic                next      :temp,2
Vadc                next      :temp,2
                    next      :temp,2
Vportb              next      :temp,2
Vporta              next      :temp,2
                    next      :temp,2
Vscitx              next      :temp,2
Vscirx              next      :temp,2
Vscierr             next      :temp,2
Vspi                next      :temp,2
Vtpm2ovf            next      :temp,2
Vtpm2ch1            next      :temp,2
Vtpm2ch0            next      :temp,2
Vtpm1ovf            next      :temp,2
                    next      :temp,2*4
Vtpm1ch1            next      :temp,2
Vtpm1ch0            next      :temp,2
                    next      :temp,2
Vlvd                next      :temp,2
Virq                next      :temp,2
Vswi                next      :temp,2
Vreset              next      :temp,2

FLASH_DATA_SIZE     align     FLASH_PAGE_SIZE     ;round to next higher block
TRUE_ROM            equ       $E000               ; start of Flash

EEPROM              def       TRUE_ROM

#ifdef BOOTROM
                    #Error    FLASH_DATA_SIZE is too large

ROM                 def       EEPROM_END+1
ROM_END             equ       $FF9F               ; end of all flash (before NV registers and fixed vectors)

ROM_END             set       BOOTROM-1

          #if FLASH_DATA_SIZE = 8*512*2           ;8KB in 512-byte pages
?NVPROT_MASK        def       1
?NVPROT_MASK        def       ROM-1&$FE00>8

RAM                 equ       $0080               ; start of RAM
RAM_END             equ       $00FF               ; last zero-page RAM location

XRAM                equ       $0100               ; start of non-zero page RAM
XRAM_END            equ       $027F               ; last RAM location

RAM                 set       BOOTRAM_END         ; start of RAM

FLASH_START         equ       EEPROM_END+1
FLASH_END           equ       ROM_END

          #ifdef BOOT&BOOTROM
FLASH_END           set       BOOTROM-1

SERIAL_NUMBER       equ       $FFA0               ; start of optional S/N (FFA0-FFAD)

#ifndef MHZ
  #ifndef KHZ
HZ                  def       33554432            ;Cyclone 32768*1024

                    #Uses     common.inc

                    org       EEPROM


          #ifndef BOOT
                    org       NVPROT              ; NV flash protection byte
                    fcb       ?NVPROT_MASK        ; NVPROT transfers to FPROT on reset

          #ifndef NVOPT_VALUE
                    #Message  Using default NVOPT_VALUE (no vector redirection)

NVOPT_VALUE         def       %11000010           ; NVFEOPT transfers to FOPT on reset
                             ; |||||||+---------- SEC00 \ 00:secure  10:unsecure
                             ; ||||||+----------- SEC01 / 01:secure  11:secure
                             ; ||++++------------ Not Used (Always 0)
                             ; |+---------------- FNORED - Vector Redirection Disable (No Redirection)
                             ; +----------------- KEYEN - Backdoor key mechanism enable

                    org       NVOPT               ; NV flash options byte
                    fcb       NVOPT_VALUE         ; NVFEOPT transfers to FOPT on reset
;                   org       NVICSTRIM           ; NV ICS Trim Setting
;                   fcb       ??                  ; ICG trim value measured during factory test. User software optionally
;                                                 ; copies to ICGTRM during initialization.
                    org       VECTORS

                    org       RAM

                    org       XRAM

                    org       ROM

                    #MEMORY   ROM       ROM_END
                    #MEMORY   NVBACKKEY NVBACKKEY+7
                    #MEMORY   NVPROT
                    #MEMORY   NVOPT
                    #MEMORY   VECTORS   VECTORS|$00FF
                    #MEMORY   EEPROM    EEPROM_END
          #ifdef CRC_LOCATION
                    #MEMORY   CRC_LOCATION CRC_LOCATION+1